w49f201 Winbond Electronics Corp America, w49f201 Datasheet

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w49f201

Manufacturer Part Number
w49f201
Description
128k X 16 Cmos Flash Memory
Manufacturer
Winbond Electronics Corp America
Datasheet
GENERAL DESCRIPTION
The W49F201 is a 2-megabit, 5-volt only CMOS flash memory organized as 128K
device can be programmed and erased in-system with a standard 5V power supply. A 12-volt V
not required. The unique cell architecture of the W49F201 results in fast program/erase operations
with extremely low current consumption (compared to other comparable 5-volt flash memory
products). The device can also be programmed and erased using standard EPROM programmers.
FEATURES
Single 5-volt operations:
Fast Program operation:
Fast Erase operation: 60 mS (typ.)
Fast Read access time: 45/55 nS
Endurance: 1K/10K cycles (typ.)
Ten-year data retention
Hardware data protection
Sector configuration
One 8K words boot block with lockout
Two 8K words parameter blocks
One 104K words (208K bytes) Main Memory
5-volt Read/Erase/Program
Word-by-Word programming: 50 S (max.)
protection
Array Blocks
128K
- 1 -
16 CMOS FLASH MEMORY
Low power consumption
Automatic program and erase timing with
internal V
End of program or erase detection
Latched address and data
TTL compatible I/O
JEDEC standard word-wide pinouts
Available packages: 44-pin SOP, 48-pin TSOP
Active current: 25 mA (typ.)
Standby current: 20 A (typ.)
Toggle bit
Data polling
Preliminary W49F201
PP
generation
Publication Release Date: June 1999
16 bits. The
Revision A1
PP
is

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w49f201 Summary of contents

Page 1

... The W49F201 is a 2-megabit, 5-volt only CMOS flash memory organized as 128K device can be programmed and erased in-system with a standard 5V power supply. A 12-volt V not required. The unique cell architecture of the W49F201 results in fast program/erase operations with extremely low current consumption (compared to other comparable 5-volt flash memory products) ...

Page 2

... NC 9 TSOP RESET Preliminary W49F201 BLOCK DIAGRAM RESET CONTROL A9 41 A10 40 WE A11 39 A12 RESET 38 37 A13 36 A14 A15 35 A16 34 NC ...

Page 3

... FUNCTIONAL DESCRIPTION Read Mode The read operation of the W49F201 is controlled by CE and OE, both of which have to be low for the host to obtain data from the outputs used for device selection. When CE is high, the chip is de-selected and only standby power will be consumed the output control and is used to gate data to the output pins ...

Page 4

... Write Status Detection 7 The W49F201 includes a data polling feature to indicate the end of a program or erase cycle. When the W49F201 is in the internal program or erase cycle, any attempt to read DQ loaded will receive the complement of the true data. Once the program or erase cycle is completed, DQ will show the true data ...

Page 5

... Write Status Detection 6 In addition to data polling, the W49F201 provides another method for determining the end of a program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ produce alternating 0's and 1's. When the program or erase cycle is completed, this toggling between 0's and 1's will stop ...

Page 6

... OUT 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 A0 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 90 5555 AA 2AAA 55 5555 F0 XXXX Preliminary W49F201 Addr. Data Addr. Data Addr. Data 5555 AA 2AAA 55 5555 10 5555 AA 2AAA 5555 AA 2AAA 55 5555 40 30 ...

Page 7

... Pause 50 S Word Program Command Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data A0 to address 5555 Load data Din to programmed- address Pause 50 S Exit - 7 - Preliminary W49F201 DATA AAH 55H A0H Programmed-data Publication Release Date: June 1999 Revision A1 ...

Page 8

... BYTE SEQUENCE 1 Write 2 Write 3 Write 4 Write 5 Write 6 Write Chip Erase Acquisition Flow Notes for chip erase: Data Format: DQ15-DQ8: Don't Care; DQ7 DQ0 (Hex) Address Format: A14 A0 (Hex) Preliminary W49F201 ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH 5555H Pause 200 mS Load data AA to ...

Page 9

... Address Format: A14 A0 (Hex 03XXX for parameter block1 SA = 05XXX for parameter block2 SA = 1FXXX - for Main Memory Block when Boot Block lockout feature is activated - for both Boot Block and Main Memory Block when Boot Block lockout feature is inactivated Preliminary W49F201 ADDRESS 5555H 2AAAH 5555H 5555H ...

Page 10

... Mode (3) (2) Read address = 0000 data = 00DA (2) Read address = 0001 data = 00AE (4) Read address = 0002 data in DQ0 =1/0 ; device code is read for Preliminary W49F201 SOFTWARE PRODUCT DETECTION EXIT (7) ADDRESS DATA 5555H AAH 2AAAH 55H 5555H F0H Pause 10 S Product Identification Exit(7) ...

Page 11

... Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 40 to address 5555 Pause 200 mS Exit - 11 - Preliminary W49F201 Publication Release Date: June 1999 Revision A1 ...

Page 12

... DQs open IH Other inputs = -0.3V, all DQs open DD Other inputs = V -0.3V/GND GND GND to V OUT 2 -0 Preliminary W49F201 RATING UNIT -0 +70 -65 to +150 -0 +1 +1.0 DD -0.5 to 12.5 LIMITS MIN. TYP. MAX 100 - - 10 ...

Page 13

... CONDITIONS I/O I 3.0V < 1.5V/1.5V 1 TTL Gate and C +5V D OUT 30 pF (Including Jig and Scope) Output 1.5V 1.5V Test Point Test Point - 13 - Preliminary W49F201 TYPICAL UNIT 100 5 mS MAX. UNIT CONDITIONS = 1.8K 1.3K Publication Release Date: June 1999 Revision A1 S ...

Page 14

... OHZ SYMBOL OES T OEH WPH and (b) low level signal's reference level Preliminary W49F201 W49F201-55 MAX. MIN. MAX MIN ...

Page 15

... CE to Toggle Bit Output Delay WE High to OE Low for Toggle Bit Hardware Reset Timing Parameters PARAMETER RESET Pulse Width RESET High Time Before Read(1) Note: 1. The parameters are characterized only and is not 100% tested. Preliminary W49F201 SYM. W49F201-45 MIN. MAX ...

Page 16

... TIMING WAVEFORMS Read Cycle Timing Diagram Address A16 High-Z DQ15-0 Controlled Command Write Cycle Timing Diagram WE Address A16 DQ15-0 Preliminary W49F201 OLZ T CLZ T OH Data Valid OES Data Valid ...

Page 17

... OES High Z Data Valid Word Program Cycle 2AAA 5555 Address 5555 WPH T WP Word 0 Word 1 Word Preliminary W49F201 T CPH T OEH Data- Internal Write Start Word 3 Publication Release Date: June 1999 Revision A1 ...

Page 18

... Timing Waveforms, continued Polling Timing Diagram DATA Address A16 DQ7 Toggle Bit Timing Diagram Address A16 DQ6 CEP T OEHP T OEP OEHT Preliminary W49F201 OES OES ...

Page 19

... Six-word code for 5V-only software chip erase 5555 5555 2AAA 5555 2AAA XX55 XX80 XXAA XXAA XX55 WPH SW0 SW2 SW3 SW1 SW4 - 19 - Preliminary W49F201 5555 XX40 T EC SW5 5555 XX10 T EC Internal Erase starts SW5 Publication Release Date: June 1999 Revision A1 ...

Page 20

... XX80 XXAA XXAA WPH SW0 SW2 SW3 SW4 SW1 command sequence. If read command is asserted during the 4-word command sequence, then the device will return to read mode(abort write Sector Address Preliminary W49F201 SA XX30 XX55 T EC Internal Erase starts SW5 ...

Page 21

... TSOP ( 200 (CMOS) 44-pin SOP 50 200 (CMOS) 44-pin SOP 50 200 (CMOS) 48-pin TSOP ( 200 (CMOS) 48-pin TSOP ( Preliminary W49F201 PACKAGE CYCLE 20 mm) 20 mm) 20 mm) 20 mm) Publication Release Date: June 1999 Revision 10K 10K ...

Page 22

... L1 44-pin SOP SEATING PLANE Preliminary W49F201 Dimension in mm Dimension in Inches Symbol MIN. NOM. MIN. NOM. MAX. MAX. 1.20 0.047 A 0.05 0.002 A1 0.95 1.00 1.05 0.037 0.039 0.041 A2 18.3 18.4 18.5 0.720 0.724 0.728 D 19.8 0.780 0.787 0.795 20 ...

Page 23

... Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502 Note: All data and specifications are subject to change without notice. Preliminary W49F201 PAGE - Renamed from W29F201C Winbond Electronics (H.K.) Ltd. Winbond Electronics North America Corp. Winbond Memory Lab. ...

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