w27e520 Winbond Electronics Corp America, w27e520 Datasheet - Page 2

• Manufacturer Part Number: w27e520
• Description: 64k X 8 Electrically Erasable Eprom
• Manufacturer: Winbond Electronics Corp America

FUNCTIONAL DESCRIPTION
Read Mode
Unlike conventional UVEPROMs, which has CE and OE
has one OE/V
address A[7:0] to be latched in the chip when it goes from high to low, so that the same bus can be
used to output data during read mode. i.e. lower address A[7:0] and data bus DQ[7:0] are multiplexed.
address access time (T
the outputs T
Erase Mode
The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs,
which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half
an hour), the W27E520 uses electrical erasure. Generally, the chip can be erased within 100 mS by
using an EPROM writer with a special erase algorithm.
There are two ways to enter Erase mode. One is to raise OE /V
A9 = V
low or high. Pulsing ALE high starts the erase operation. The other way is somewhat like flash, by
programming two consecutive commands into the device and then enter Erase mode. The two
commands are loading Data = AA(hex) to Addr. = 5555(hex) and Data = 10(hex) to Addr. =
2AAA(hex). Be careful to note that the ALE pulse widths of these two commands are different: One is
50uS, while the other is 100mS. Please refer to the Smart Erase Algorithm 1 & 2.
Erase Verify Mode
The device will enter the Erase Verify Mode automatically after Erase Mode. Only power down the
device can force the device enter Normal Read Mode again.
Program Mode
Programming is the only way to change cell data from "1" to "0." The program mode is entered when
the input pins equal the desired inputs. Pulsing ALE high starts the programming operation.
Program Verify Mode
The device will enter the Program Verify Mode automatically after Program Mode. Only power down
the device can force the device enter Normal Read Mode again.
Erase/Program Inhibit
Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different
data. When ALE low, erasing or programming of non-target chips is inhibited, so that except for the
ALE and OE /V
Standby Mode
The standby mode significantly reduces V
keep high. In standby mode, all outputs are in a high impedance state.
OE/V
OE/V
PP
PP
HH
is raised to V
controls the output buffer to gate data to the output pins. When addresses are stable, the
(13V), A10 = high A8&A11 = low, and all other address pins include AD[7:0] keep at fixed
OE
PP
after the falling edge of OE/V
PP
pins, the W27E520 may have common inputs.
and one ALE (address_latch_enable) control functions. The ALE makes lower
PP
ACC
(13V), V
) is equal to the delay from ALE to output (T
DD
= V
DP
DD
(6.5V), the address pins equal the desired addresses, and
current. This mode is entered when ALE and OE /V
PP
- 2 -
, if T
ACC
and T
two control functions, the W27E520
CE
PP
timings are met.
to V
CE
PE
), and data are available at
(13V), V
DD
W27E520
= V
DE
(6.5V),
PP