km29w32000ts Samsung Semiconductor, Inc., km29w32000ts Datasheet
km29w32000ts
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km29w32000ts Summary of contents
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... KM29W32000TS Document Title Bit NAND Flash Memory Revision History Revision No. History 0.0 Initial issue. 1.0 Data Sheet, 1998 1.1 Data Sheet, 1999 1) Added CE don’ t care mode during the data-loading and reading The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications ...
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... KM29W32000TS Bit NAND Flash Memory FEATURES Voltage Supply : 2.7V ~ 5.5V Organization - Memory Cell Array : (4M + 128K)bit x 8bit - Data Register : (512 + 16)bit x8bit Automatic Program and Erase - Page Program : (512 + 16)Byte - Block Erase : (8K + 256)Byte - Status Register 528-Byte Page Read Operation - Random Access : 10 s(Max.) - Serial Page Access : 50ns(Min.) ...
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... KM29W32000TS Figure 1. FUNCTIONAL BLOCK DIAGRAM Command Figure 2. ARRAY ORGANIZATION 32M : 8K Row 1st half Page Register (=512 Block) (=256 Bytes) 512B Column Page Register I/O 0 1st Cycle A 0 2nd Cycle A 9 3rd Cycle A 17 NOTE : Column Address : Starting Address of the Register. ...
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... KM29W32000TS PRODUCT INTRODUCTION The KM29W32000 is a 33Mbit(34,603,008 bit) memory organized as 8192 rows by 528 columns. Spare sixteen columns are located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made cells that are serially connected to form a NAND structure ...
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... KM29W32000TS PIN DESCRIPTION Command Latch Enable(CLE) The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal. Address Latch Enable(ALE) The ALE input controls the path activation for address and input data to the internal address/data register. ...
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... KM29W32000TS ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative Temperature Under Bias Storage Temperature Short Circuit Output Current NOTE : 1. Minimum DC voltage is -0.3V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet ...
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... KM29W32000TS AC TEST CONDITION ( =2.7V ~ 5.5V unless otherwise noted Parameter Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load CAPACITANCE (T =25 C, Vcc=5.0V, f=1.0MHz) A Item Input/Output Capacitance Input Capacitance NOTE : Capacitance is periodically sampled and not 100% tested. ...
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... KM29W32000TS AC Timing Characteristics for Command / Address / Data Input Parameter CLE Set-up Time CLE Hold Time CE Setup Time CE Hold Time WE Pulse Width ALE Setup Time ALE Hold Time Data Setup Time Data Hold Time Write Cycle Time WE High Hold Time AC Characteristics for Operation ...
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... KM29W32000TS Pointer Operation of KM29W32000 The KM29W32000 has three read modes to set the destination of the pointer. The pointer is set to "A" area by the "00h" command, to "B" area by the "01" command, and to "C" area by the "50h" command. Table 1 shows the destination of the pointer, and figure 2 shows the block diagram of its operations ...
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... KM29W32000TS System Interface Using CE don’ t -care. For a easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal 528byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and read- ing would provide significant savings in power consumption ...
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... KM29W32000TS * Command Latch Cycle CLE CE WE ALE I Address Latch Cycle CLE CE WE ALE I CLS CLH ALS ALH Command t CLS ALS FLASH MEMORY ...
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... KM29W32000TS * Input Data Latch Cycle CLE CE t ALS ALE Sequential Out Cycle after Read R/B NOTES : Transition is measured 200mV from steady state voltage with load DIN 1 DIN 0 (CLE=L, WE=H, ALE= ...
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... KM29W32000TS * Status Read Cycle CLE I READ1 OPERATION (READ ONE PAGE) CLE ALE I/O ~ 00h or 01h Column Address R/B t CLS t CLH t CLS WHR 70H AR2 Dout N Dout N ...
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... KM29W32000TS READ1 OPERATION (INTERCEPTED BY CE) CLE CE WE ALE RE 00h or 01h I Column Address R/B READ2 OPERATION (READ ONE PAGE) CLE CE WE ALE RE 50H A I R/B M Address AR2 Dout Page(Row) Address Busy ...
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... KM29W32000TS SEQUENTIAL ROW READ OPERATION CLE CE WE ALE RE 00H I R/B M PAGE PROGRAM OPERATION CLE ALE RE 80H I Sequential Data Column Input Command Address R/B Dout Dout N+1 Busy Din Din ...
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... KM29W32000TS BLOCK ERASE OPERATION CLE ALE RE I/O ~ 60H Block Address R/B Auto Block Erase Setup Command SUSPEND & RESUME OPERATION DURING BLOCK ERASE CLE CE WE ALE RE Block Address I/O ~ 60H R/B Auto Block Erase Setup Command (ERASE ONE BLOCK) ...
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... KM29W32000TS MANUFACTURE & DEVICE ID READ OPERATION CLE CE WE ALE RE I/O ~ 90H 0 7 Read ID Command t REAID 00H Maker Code 17 FLASH MEMORY ECH E3H Device Code ...
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... KM29W32000TS DEVICE OPERATION PAGE READ Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00H to the command reg- ister along with three address cycles. Once the command is latched, it does not need to be written for the following page read opera- tion ...
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... KM29W32000TS Figure 4. Read2 Operation CLE CE WE ALE R/B RE 50H Start Add.(3Cycle) I & Don't Care) Figure 5. Sequential Row Read1 Operation R/B I 00H Start Add.(3Cycle) 01H & (SE=L, 00H Command) 1st half array 2nd half array ...
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... KM29W32000TS Figure 6. Sequential Read2 Operation R/B I 50H Start Add.(3Cycle & Don't Care) PAGE PROGRAM The device is programmed basically on a page basis, but it does allow multiple partial page programming of a byte or consecutive bytes up to 528 single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed ten ...
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... KM29W32000TS BLOCK ERASE The Erase operation can erase on a block(8K Byte) basis. Block address loading is accomplished in two cycles initiated by an Erase Setup command(60H). Only address A The Erase Confirm command(D0H) following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution ensures that memory contents are not accidentally erased due to external noise conditions ...
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... KM29W32000TS READ STATUS The device contains a Status Register which may be read to find out whether program or erase operation is complete, and whether the program or erase operation completed successfully. After writing 70H command to the command register, a read cycle outputs the contents of the Status Register to the I/O pins on the falling edge RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired ...
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... KM29W32000TS RESET The device offers a reset feature, executed by writing FFH to the command register. When the device is in Busy state during random read, program or erase modes, the reset operation will abort these operation. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. Internal address registers are cleared to "0"s and data registers to " ...
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... KM29W32000TS READY/BUSY The device has a R/ output that provides a hardware method of indicating the completion of a page program, erase and random B read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command reg- ister or random read is begin after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied ...
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... KM29W32000TS PACKAGE DIMENSIONS 44(40) LEAD PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(II) 44(40) - TSOP2 - 400F #44(40) #1 18.81 0.741 18.41 0.10 0.725 0.004 0.805 0.35 0.10 0.032 0.014 0.004 #23(21) #22(20) Max. 0.80 0.0315 25 FLASH MEMORY Unit :mm/Inch 0~8 0.25 0.010 TYP 0.50 0.020 +0.10 0.15 -0.05 +0.004 0.006 -0.002 0.10 MAX 0.004 ...