km29u128t Samsung Semiconductor, Inc., km29u128t Datasheet

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km29u128t

Manufacturer Part Number
km29u128t
Description
16m X 8 Bit Nand Flash Memory
Manufacturer
Samsung Semiconductor, Inc.
Datasheet

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Part Number:
KM29U128T
Manufacturer:
SAMSUNG
Quantity:
11 350
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Document Title
Revision History
KM29U128T, KM29U128IT
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
Revision No.
16M x 8 Bit NAND Flash Memory
0.0
1.0
1.1
History
Initial issue.
1) Changed t
2) Changed t
3) Changed Input and Output Timing Level 0.8V and 2.0V
1) Changed t
2) Changed Nop : 10 cycles(Max.)
3) Added CE don’ t care mode during the data-loading and reading
PROG
BERS
R
Parameter : 7 s(Max.)
Parameter : 4ms(Max.)
Parameter : 1ms(Max.)
Spare Array 3 cycles(Max.)
Main Array
10 s(Max.)
1
3ms(Max.)
500 s(Max.)
2 cycles(Max.)
1.5V
Draft Date
April 10th 1998
July 14th 1998
April 10th 1999
FLASH MEMORY
Remark
Preliminary
Final
Final

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km29u128t Summary of contents

Page 1

... KM29U128T, KM29U128IT Document Title 16M x 8 Bit NAND Flash Memory Revision History Revision No. History 0.0 Initial issue. 1.0 1) Changed t PROG 2) Changed t BERS 3) Changed Input and Output Timing Level 0.8V and 2.0V 1.1 1) Changed t Parameter : 7 s(Max Changed Nop : 10 cycles(Max.) 3) Added CE don’ t care mode during the data-loading and reading The attached datasheets are prepared and approved by SAMSUNG Electronics ...

Page 2

... KM29U128T, KM29U128IT 16M x 8 Bit NAND Flash Memory FEATURES Voltage supply : 2.7V~3.6V Organization - Memory Cell Array : (16M + 512K)bit x 8bit - Data Register : (512 + 16)bit x8bit Automatic Program and Erase - Page Program : (512 + 16)Byte - Block Erase : (16K + 512)Byte 528-Byte Page Read Operation - Random Access : 10 s(Max.) - Serial Page Access : 50ns(Min ...

Page 3

... KM29U128T, KM29U128IT Figure 1. FUNCTIONAL BLOCK DIAGRAM X-Buffers Latches & Decoders Y-Buffers Latches & Decoders Command Command CE Control Logic RE & High Voltage WE Generator CLE ALE WP Figure 2. ARRAY ORGANIZATION 32K Row 1st half Page Register (=1024 Block) ...

Page 4

... KM29U128T, KM29U128IT PRODUCT INTRODUCTION The KM29U128 is a 132Mbit(138,412,032 bit) memory organized as 32,768 rows by 528 columns. Spare sixteen columns are located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating data trans- fer between the I/O buffers and memory during page read and page program operations. The memory array is made cells that are serially connected to form a NAND structure ...

Page 5

... KM29U128T, KM29U128IT PIN DESCRIPTION Command Latch Enable(CLE) The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal. Address Latch Enable(ALE) The ALE input controls the path activation for address and input data to the internal address/data register ...

Page 6

... Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED OPERATING CONDITIONS (Voltage reference to GND, KM29U128T Parameter Supply Voltage ...

Page 7

... KM29U128T, KM29U128IT VALID BLOCK Parameter Valid Block Number NOTE : 1. The KM29U128 may include invalid blocks. Invalid blocks are defined as blocks that contain one or more bad bits. Do not try to access these invalid blocks for program and erase. During its lifetime of 10 years and/or 1million program/erase cycles,the minimum number of valid blocks are guaran- teed though its initial number could be reduced ...

Page 8

... KM29U128T, KM29U128IT AC Timing Characteristics for Command / Address / Data Input Parameter CLE Set-up Time CLE Hold Time CE Setup Time CE Hold Time WE Pulse Width ALE Setup Time ALE Hold Time Data Setup Time Data Hold Time Write Cycle Time WE High Hold Time AC Characteristics for Operation ...

Page 9

... KM29U128T, KM29U128IT NAND Flash Technical Notes Invalid Block(s) Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. Typically, an invalid block will contain a single bad bit. The information regarding the invalid block( called as the invalid block informa- tion ...

Page 10

... KM29U128T, KM29U128IT NAND Flash Technical Notes (Continued) Error in write or read operation Over its life time, the additional invalid blocks may occur. Through the tight process control and intensive testing, Samsung mini- mizes the additional block failure rate, which is projected below 0.1% up until 1million program/erase cycles. Refer to the qualification report for the actual data ...

Page 11

... KM29U128T, KM29U128IT NAND Flash Technical Notes (Continued) Erase Flow Chart Start Write 60H Write Block Address Write D0H Write 70H SR R Erase Error SR Erase Completed : If erase operation results in an error, map out * the failing block and replace it with another block. ...

Page 12

... KM29U128T, KM29U128IT Pointer Operation of KM29U128 The KM29U128 has three read modes to set the destination of the pointer. The pointer is set to "A" area by the "00h" command, to "B" area by the "01" command, and to "C" area by the "50h" command. Table 1 shows the destination of the pointer, and figure 2 shows the block diagram of its operations ...

Page 13

... KM29U128T, KM29U128IT System Interface Using CE don’ t -care. For a easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal 528byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and read- ing would provide significant savings in power consumption ...

Page 14

... KM29U128T, KM29U128IT * Command Latch Cycle CLE CE WE ALE I Address Latch Cycle CLE CE WE ALE I CLH CLS ALH ALS Command t CLS ALS FLASH MEMORY t WC ...

Page 15

... KM29U128T, KM29U128IT * Input Data Latch Cycle CLE CE t ALS ALE I Sequential Out Cycle after Read R/B NOTES : Transition is measured 200mV from steady state voltage with load DIN 0 DIN 1 (CLE=L, WE=H, ALE=L) ...

Page 16

... KM29U128T, KM29U128IT * Status Read Cycle CLE I READ1 OPERATION (READ ONE PAGE) CLE ALE RE 00h or 01h I Column Address R/B t CLS t CLS t CLH WHR 70H AR2 Dout N Dout N+1 ...

Page 17

... KM29U128T, KM29U128IT READ1 OPERATION (INTERCEPTED BY CE) CLE CE WE ALE RE 00h or 01h I Column Address R/B READ2 OPERATION (READ ONE PAGE) CLE CE WE ALE RE I/O ~ 50H R/B M Address AR2 Dout Page(Row) Address Busy ...

Page 18

... KM29U128T, KM29U128IT SEQUENTIAL ROW READ OPERATION CLE CE WE ALE RE 00H I R/B M PAGE PROGRAM OPERATION CLE ALE RE I/O ~ 80H Sequential Data Column Input Command Address R/B Dout Dout N+1 Ready Busy Din ...

Page 19

... KM29U128T, KM29U128IT BLOCK ERASE OPERATION CLE ALE RE I/O ~ 60H Page(Row) Address R/B Auto Block Erase Setup Command MANUFACTURE & DEVICE ID READ OPERATION CLE CE WE ALE RE 90H I Read ID Command (ERASE ONE BLOCK DOH 23 Busy Erase Command ...

Page 20

... KM29U128T, KM29U128IT DEVICE OPERATION PAGE READ Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00H to the command reg- ister along with three address cycles. Once the command is latched, it does not need to be written for the following page read opera- tion ...

Page 21

... KM29U128T, KM29U128IT Figure 4. Read2 Operation CLE CE WE ALE R/B RE 50H Start Add.(3Cycle) I & Don t Care) Figure 5. Sequential Row Read1 Operation R/B I 00H Start Add.(3Cycle) 01H & (SE=L, 00H Command) 1st half array 2nd half array ...

Page 22

... KM29U128T, KM29U128IT Figure 6. Sequential Row Read2 Operation R/B I 50H Start Add.(3Cycle & Don t Care) PAGE PROGRAM The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte or consecutive bytes up to 528 single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation should not exceed 2 for main array and 3 for spare array ...

Page 23

... KM29U128T, KM29U128IT BLOCK ERASE The Erase operation is done on a block(16K Byte) basis. Block address loading is accomplished in two cycles initiated by an Erase Setup command(60H). Only address A block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. ...

Page 24

... KM29U128T, KM29U128IT READ ID The device contains a product identification mode, initiated by writing 90H to the command register, followed by an address input of 00H. Two read cycles sequentially output the manufacture code(ECH), and the device code (73H) respectively. The command regis- ter remains in Read ID mode until further commands are issued to it. Figure 9 shows the operation sequence. ...

Page 25

... KM29U128T, KM29U128IT READY/BUSY The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command reg- ister or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied ...

Page 26

... KM29U128T, KM29U128IT PACKAGE DIMENSIONS 48-PIN LEAD PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE( TSOP1 - 1220F #1 #24 ¡Æ 0~8 0.45~0.75 0.018~0.030 20.00 0.20 0.787 0.008 18.40 0.10 0.724 0.004 26 FLASH MEMORY Unit :mm/Inch #48 #25 1.00 0.05 0.05 0.039 0.002 0.002 1.20 MAX 0.047 0. 0.020 MIN ...

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