k7i161882b Samsung Semiconductor, Inc., k7i161882b Datasheet
k7i161882b
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k7i161882b Summary of contents
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... K7I163682B K7I161882B 18Mb DDRII SRAM Specification 165FBGA with Pb & Pb-Free INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ...
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... K7I163682B K7I161882B Document Title 512Kx36-bit, 1Mx18-bit DDRII CIO b2 SRAM Revision History Rev. No. History 0.0 1. Initial document. 0.1 1. Add the speed bin (-33, -30) 2. Delete the speed bin (-25, -13) 0.2 1. Change the Boundary scan exit order. 2. Correct the Overshoot and Undershoot timing diagram. 0.3 1. Add the speed bin (-25) ...
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... WRITE DRIVER 18 512Kx36 (1Mx18) MEMORY ARRAY SELECT OUTPUT CONTROL - 3 - Part Cycle Access Number Time Time K7I163682B-E(F)C(I)30 3.3 K7I163682B-E(F)C(I)25 4.0 K7I163682B-E(F)C(I)20 5.0 K7I163682B-E(F)C(I)16 6.0 K7I161882B-E(F)C(I)30 3.3 K7I161882B-E(F)C(I)25 4.0 K7I161882B-E(F)C(I)20 5.0 K7I161882B-E(F)C(I)16 6 (or 18) (or 36) (or 18) (Echo Clock out) Rev. 5.0 July 2006 Unit 0.45 ns 0.45 ns 0.45 ns 0.50 ns 0.45 ns 0.45 ns 0. CQ, CQ ...
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... K7I163682B K7I161882B PIN CONFIGURATIONS (TOP VIEW SA DQ27 DQ18 DQ28 D NC DQ29 DQ19 DQ20 F NC DQ30 DQ21 G NC DQ31 DQ22 H Doff V V REF DDQ DQ32 DQ23 L NC DQ33 DQ24 DQ34 N NC DQ35 ...
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... K7I163682B K7I161882B PIN CONFIGURATIONS (TOP VIEW) K7I161882B(1Mx18 SA DQ9 DQ10 DQ11 F NC DQ12 DQ13 H Doff V V REF DDQ DQ14 L NC DQ15 DQ16 P NC ...
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... The K7I163682B and K7I1161882B are 18,874,368-bits DDR Common I/O Synchronous Pipelined Burst SRAMs. They are organized as 524,288 words by 36bits for K7I163682B and 1,048,576 words by 18 bits for K7I161882B for K7I160882B. Address, data inputs, and all control signals are synchronized to the input clock ( ...
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... Circuitry automatically resets the DLL when absence of input clock is detected. Single Clock Mode K7I163682B and K7I161882B can be operated with the single clock pair K and K, instead for output clocks. To operate these devices in single clock mode, C and C must be tied high during power up and must be maintained high during operation. After power up, this device can′ ...
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... K7I163682B K7I161882B LINEAR BURST SEQUENCE TABLE BURST SEQUENCE First Address Second Address LOAD LOAD DDR READ Notes: 1. Internal burst counter is fixed as 2-bit linear, i.e. when first address is A0+0, next internal burst address is A0+1. 2. "LOAD" refers to read new address active status with LD=Low, "LOAD" refers to read new address inactive status with LD=High. ...
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... K7I163682B K7I161882B TRUTH TABLES SYNCHRONOUS TRUTH TABLE K LD R/W Stopped X ↑ H ↑ L ↑ L Notes means "Don′t Care". 2. The rising edge of clock is symbolized by ( ↑ Before enter into clock stop status, all pending read and write operations will be completed. WRITE TRUTH TABLE ...
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... K7I163682B K7I161882B ABSOLUTE MAXIMUM RATINGS* PARAMETER Voltage on V Supply Relative Voltage on V Supply Relative to V DDQ Voltage on Input Pin Relative Storage Temperature Operating Temperature Storage Temperature Range Under Bias *Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied ...
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... K7I163682B K7I161882B AC ELECTRICAL CHARACTERISTICS PARAMETER Input High Voltage Input Low Voltage Notes: 1. This condition is for AC function test only, not for AC parameter test maintain a valid level, the transition edge of the input must : a) Sustain a constant slew rate from the current AC level through the target AC level, V ...
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... K7I163682B K7I161882B AC TIMING CHARACTERISTICS PARAMETER SYMBOL Clock Clock Cycle Time ( Clock Phase Jitter ( Clock High Time ( Clock Low Time ( Clock to Clock (K↑ → K↑, C↑ → C↑) Clock to data clock (K↑ → C↑, K↑→ C↑) ...
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... K7I163682B K7I161882B PIN CAPACITANCE PRMETER Address Control Input Capacitance Input and Output Capacitance Clock Capacitance Note: 1. Parameters are tested with RQ=250Ω and V 2. Periodically sampled and not 100% tested. THERMAL RESISTANCE PRMETER Junction to Ambient Junction to Case Note: Junction temperature is a function of on-chip power dissipation, package thermal impedance, mounting site temperature and mounting site x θ ...
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... K7I163682B K7I161882B TIMING WAVE FORMS OF READ, WRITE AND NOP NOP READ READ (burst of 2) (burst KHKL KHKH K t KLKH t t IVKH KHIX LD R CHQV t t KHCH CHQX1 CHCQX CHCQV NOTE 1. Q refers to output from address ...
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... K7I163682B K7I161882B IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG This part contains an IEEE standard 1149.1 Compatible Test Access Port(TAP). The package pads are monitored by the Serial Scan circuitry when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. Internal data is not driven out of the SRAM under JTAG control ...
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... K7I163682B K7I161882B SCAN REGISTER DEFINITION Part Instruction Register 512Kx36 3 bits 1Mx18 3 bits ID REGISTER DEFINITION Revision Number Part (31:29) 512Kx36 000 1Mx18 000 Note : Part Configuration /def=001 for 18Mb, /wx=11 for x36, 10 for x18 /t=1 for DLL Ver., 0 for non-DLL Ver. /q=1 for QDR, 0 for DDR /b=1 for 4Bit Burst, 0 for 2Bit Burst /s=1 for Separate I/O, 0 for Common I/O ...
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... K7I163682B K7I161882B JTAG DC OPERATING CONDITIONS Parameter Power Supply Voltage Input High Level Input Low Level Output High Voltage(I =-2mA) OH Output Low Voltage(I =2mA) OL Note: 1. The input level of SRAM pin is to follow the SRAM DC specification JTAG AC TEST CONDITIONS Parameter Input High/Low Level ...
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... K7I163682B K7I161882B 165 FBGA PACKAGE DIMENSIONS 13mm x 15mm Body, 1.0mm Bump Pitch, 11x15 Ball Array Symbol Value Units 13 ± 0 ± 0.1 B 1.3 ± 0.1 C 0.35 ± 0.05 D 512Kx36 & 1Mx18 DDRII CIO b2 SRAM Note Symbol Top View ...