gvt71256d36 ETC-unknow, gvt71256d36 Datasheet - Page 8

• Manufacturer Part Number: gvt71256d36
• Description: 256k 36/512k Synchronous Sram
• Manufacturer: ETC-unknow

TRUTH TABLE
Note:
PARTIAL TRUTH TABLE FOR READ/WRIT E
Note: For X18 product, There are only BWa# and BWb#.
May 18, 199 9
Rev. 5/99
GALVANTECH
OPERATION
Deselected Cycle, Power Dow n
Deselected Cycle, Power Dow n
Deselected Cycle, Power Dow n
Deselected Cycle, Power Dow n
Deselected Cycle, Power Dow n
READ Cycle, Begin Burs t
READ Cycle, Begin Burs t
WRITE Cycle, Begin Burs t
READ Cycle, Begin Burs t
READ Cycle, Begin Burs t
READ Cycle, Continue Burs t
READ Cycle, Continue Burs t
READ Cycle, Continue Burs t
READ Cycle, Continue Burs t
WRITE Cycle, Continue Burs t
WRITE Cycle, Continue Burs t
READ Cycle, Suspend Burs t
READ Cycle, Suspend Burs t
READ Cycle, Suspend Burs t
READ Cycle, Suspend Burs t
WRITE Cycle, Suspend Burs t
WRITE Cycle, Suspend Burs t
READ
READ
WRITE one byte
WRITE all bytes
WRITE all bytes
FUNCTIO N
1.
2. BWa# enables write to DQa. BWb# enables write to DQb. BWc# enables write to DQc. BWd# enables write to DQd .
3. All inputs except OE# must meet setup and hold times around the rising edge (LOW to HIGH) of CLK .
4.
5. For a write operation following a read operation, OE# must be HIGH before the input data required setup time plus High-Z time
6. This device contains circuitry that will ensure the outputs will be in High-Z during power-up .
7. ADSP# LOW along with chip being selected always initiates a READ cycle at the L-H edge of CLK. A WRITE cycle can be
X means “don’t care.” H means logic HIGH. L means logic LOW.
For X36 product, WRITE# = L means [BWE# + BWa#*BWb#*BWc#*BWd#]*GW# equals LOW. WRITE# = H means
[BWE# + BWa#*BWb#*BWc#*BWd#]*GW# equals HIGH.
For X18 product, WRITE# = L means [BWE# + BWa#*BWb#]*GW# equals LOW. WRITE# = H means [BWE# +
BWa#*BWb#]*GW# equals HIGH.
Suspending burst generates wait cycle.
for OE# and staying HIGH throughout the input data hold time .
performed by setting WRITE# LOW for the CLK L-H edge of the subsequent wait cycle. Refer to WRITE timing diagram for
clarification.
GW#
H
H
H
H
L
ADDRESS
External
External
External
External
External
Current
Current
Current
Current
Current
Current
None
None
None
None
None
USED
Next
Next
Next
Next
Next
Next
BWE#
, INC.
H
X
L
L
L
CE#
H
X
X
H
H
X
H
X
X
H
H
X
H
L
L
L
L
L
L
L
L
L
BWa#
CE2#
X
H
X
L
L
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
L
L
L
L
256K X 36/512K X 18 SYNCHRONOUS SRAM
CE2
X
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
L
BWb#
8
X
H
H
X
L
ADSP# ADSC#
X
H
H
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
L
L
L
L
BWc#
H
H
X
X
L
H
H
H
H
H
H
H
H
H
H
H
H
L
X
X
L
L
X
X
L
L
L
GVT71256D36/GVT71512D18
ADV#
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
BWd#
L
L
L
L
L
L
Galvantech, Inc. reserves the right to change products or specifications without notice
X
H
H
X
L
WRITE#
H
H
H
H
H
H
H
H
H
H
X
X
X
X
X
X
X
L
L
L
L
L
OE#
X
X
X
X
X
H
X
H
H
H
X
X
H
H
X
X
L
L
L
L
L
L
CLK
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
L-H
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
DQ
Q
D
Q
Q
Q
D
D
Q
Q
D
D
.