w49v002a Winbond Electronics Corp America, w49v002a Datasheet
w49v002a
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w49v002a Summary of contents
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... The W49V002A -megabit, 3.3-volt only CMOS flash memory organized as 256K device can be programmed and erased in-system with a standard 3.3V power supply. A 12-volt V not required. The unique cell architecture of the W49V002A results in fast program/erase operations with extremely low current consumption. This device can operate at two modes, Programmer bus interface mode and LPC bus interface mode ...
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... BLOCK1 32K BYTES R/#C MAIN MEMORY BLOCK2 A[10:0] 64K BYTES Program- mer DQ[7:0] MAIN MEMORY Interface BLOCK3 64K BYTES #OE MAIN MEMORY #WE BLOCK4 64K BYTES Preliminary W49V002A PIN DESCRIPTION SYMB MODE #RESET MODE GND #INIT NC NC #TBL VDD #OE(#INIT) #WE(#LFRAM) #WP NC DQ7(RSV) CLK GPI[4:0] LAD[3:0] ...
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... Revision 1.0. Through LAD[3:0] to communicate with the system chipset . Read(Write) Mode In Programmer interface mode, the read(write) operation of the W49V002A is controlled by #OE (#WE). The #OE (#WE) is held low for the host to obtain(write) data from(to) the outputs(inputs). #OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when #OE is high the LPC interface mode, the read or write is determined by the " ...
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... Write Status Detection 7 The W49V002A includes a data polling feature to indicate the end of a program or erase cycle. When the W49V002A is in the internal program or erase cycle, any attempts to read DQ loaded will receive the complement of the true data. Once the program or erase cycle is completed, DQ will show the true data. Note that DQ has been completed it becomes logical " ...
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... Block 4M Byte BIOS ROM 128K Byte BIOS ROM Registers General Purpose Inputs Register This register reads the GPI[4:0] pins on the W49V002A.This is a pass-through register which can read via memory address FFBC0100(hex). Since it is pass-through register, there is no default value. Bit Function 7-5 ...
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... SA = 3C000h to 3FFFFh for Boot Block SA = 3A000h to 3BFFFh for Parameter Block1 SA = 38000h to 39FFFh for Parameter Block2 SA = 30000h to 37FFFh for Main Memory Block1 SA = 2XXXXh for Main Memory Block2 SA = 1XXXXh for Main Memory Block3 SA = 0XXXXh for Main Memory Block4 Preliminary W49V002A #WE #RESET VIH VIH AIN VIL ...
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... Sync. N Data 2 Note: 1. For detail related LPC specification, please refer to Intel LPC spec. 1.0 or later. Preliminary W49V002A DESCRIPTION "0000b" appears on LPC bus to indicate the initial "010Xb" indicates memory read cycle; while "011xb" indicates memory write cycle. "X" mean don't have to care. ...
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... Command Codes for Byte Program BYTE SEQUENCE 0 Write 1 Write 2 Write 3 Write Byte Program Flow Chart Notes for software program code: Data Format: DQ7 DQ0 (Hex Don't Care Address Format: A14 A0 (Hex) Preliminary W49V002A ADDRESS 5555H 2AAAH 5555H Programmed-Address Byte Program Command Flow Load data AA to ...
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... BYTE SEQUENCE 1 Write 2 Write 3 Write 4 Write 5 Write 6 Write Chip Erase Acquisition Flow Notes for chip erase: Data Format: DQ7 DQ0 (Hex) Address Format: A14 A0 (Hex) Preliminary W49V002A ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH 5555H Load data AA to address 5555 Load data 55 ...
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... Data Format: DQ7 DQ0 (Hex) Address Format: A14 A0 (Hex Sector Address SA = 3C000h to 3FFFFh for Boot Block SA = 3A000h to 3BFFFh for Parameter Block1 SA = 38000h to 39FFFh for Parameter Block2 SA = 30000h to 37FFFh for Main Memory Block1 SA = 0XXXXh for Main Memory Block4 Preliminary W49V002A ADDRESS 5555H 2AAAH 5555H 5555H 2AAAH ...
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... If the DQ0 of output data is "1," the boot block programming lockout feature is activated; if the DQ0 of output data "0," the lockout feature is inactivated and the block can be programmed. (5) The device returns to standard operation mode. (6) Optional 1-write cycle (write F0 hex at XXXX address) can be used to exit the product identification/boot block lockout detection. Preliminary W49V002A SOFTWARE PRODUCT IDENTIFICATION / ENTRY DATA ...
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... Write 3 Write 4 Write 5 Write 6 Write Boot Block Lockout Enable Acquisition Flow Notes for boot block lockout enable: Data Format: DQ7 DQ0 (Hex) Address Format: A14 A0 (Hex) Preliminary W49V002A BOOT BLOCK LOCKOUT FEATURE SET ADDRESS DATA 5555H AAH 2AAAH 55H 5555H 80H ...
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... Output Leakage I LO Current Input Low Voltage V IL Input High Voltage V IH Output Low Voltage V OL Output High Voltage V OH Preliminary W49V002A TEST CONDITIONS In Read or Write mode, all DQs open Address inputs = 3.0V/0V MHz V = GND GND to V OUT 2.1 mA ...
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... OH Power-up Timing PARAMETER Power-up to Read Operation Power-up to Write Operation CAPACITANCE (V = 3.3V MHz PARAMETER I/O Pin Capacitance Input Capacitance Preliminary W49V002A TEST CONDITIONS All I = 0A, CLK = 33MHz, out in LPC mode operation. #LFRAM = 0 CLK = 33MHz, DD all inputs = 0 0 #LFRAM = 0 CLK = 33MHz, DD all inputs = 0 ...
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... PROGRAMMER INTERFACE MODE AC CHARACTERISTICS AC Test Conditions PARAMETER Input Pulse Levels Input Rise/Fall Time Input/Output Timing Level Output Load AC Test Load and Waveform D OUT 30 pF (Including Jig and Scope) Preliminary W49V002A CONDITIONS 0V to 0.9VDD < 1.5V/1.5V 1 TTL Gate and +3.3V 1.8K Input 0. ...
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... High level signal's reference level is input high and (b) low level signal's reference level is input low. Ref. to the AC testing condition. Data Polling and Toggle Bit Timing Parameters PARAMETER #OE to Data Polling Output Delay #OE to Toggle Bit Output Delay Preliminary W49V002A SYM. W49V002A MIN. MAX. T ...
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... TIMING WAVEFORMS FOR PROGRAMMER INTERFACE MODE Read Cycle Timing Diagram #RESET T RST A[10: #WE #OE High-Z DQ[7:0] Write Cycle Timing Diagram T RST #RESET A[10: #OE #WE DQ[7:0] Preliminary W49V002A T RC Column Address Row Address OLZ Column Address Row Address ...
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... Column/Row Address are mapped to the Low/High order internal address. i.e. Column Address A[10:0] are mapped to the internal A[10:0], Row Address A[6:0] are mapped to the internal A[17:11]. #DATA Polling Timing Diagram A[10:0] (Internal A[17:0 #WE #OE DQ7 Preliminary W49V002A Byte Program Cycle 5555 2AAA 5555 Programmed Address WPH WP ...
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... Note: The internal address A[17:0] are converted from external Column/Row address. Column/Row Address are mapped to the Low/High order internal address. i.e. Column Address A[10:0] are mapped to the internal A[10:0], Row Address A[6:0] are mapped to the internal A[17:11]. Preliminary W49V002A T OET Six-byte code for 3.3V-only software chip erase ...
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... Column/Row Address are mapped to the Low/High order internal address. i.e. Column Address A[10:0] are mapped to the internal A[10:0], Row Address A[6:0] are mapped to the internal A[17:11 Sector Address, Please ref. to the "Table of Command Definition" Preliminary W49V002A Six-byte code for 3.3V-only software chip erase 2AAA 5555 5555 ...
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... Reset Inactive to Input Active Note: All AC timing signals observe the following guidelines for determining setup and hold times: (a) High level signal's reference level is input high and (b) low level signal's reference level is input low. Ref. to the AC testing condition. Preliminary W49V002A CONDITIONS 0 0.2 V ...
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... Write Cycle Timing Diagram CLK #RESET #LFRAM Memory Write Start Cycle 0000b 011Xb A[31:28] A[27:24] LAD[3:0] 1 Clock 1 Clock Load Address in 8 Clocks, the address should be within the top 4MByte, FFFFFFFF to FFC00000, or within the bottom 1MByte, 000FFFFF to 000E0000. Preliminary W49V002A T CYC Address A[23:20] A[19:16] A[15:12] A[11:8] A[7:4] A[3:0] 1111b 2 Clocks T CYC ...
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... Start Cycle LAD[3:0] 0000b A[31:28] A[27:24] 011Xb 1 Clock 1 Clock All the address loaded should be within the top 4MByte,FFFFFFFF to FFC00000, or within the bottom 1MByte, 000FFFFF to 000E0000. Preliminary W49V002A Address A[27:24] A[23:20] A[19:16] X101b 0101b 0101b 0101b Load Address "5555" Clocks Write the 1st command to the device in LPC mode. ...
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... Memory Read Start Cycle 0000b LAD[3:0] 010Xb An[31:28] An[27:24] 1 Clock 1 Clock All the address loaded should be within the top 4MByte,FFFFFFFF to FFC00000, or within the bottom 1MByte, 000FFFFF to 000E0000. Preliminary W49V002A Address Dn[3:0] An[7:4] An[3:0] An[23:20] An[19:16] An[15:12] An[11:8] Load Data "Dn" Load Address "An" Clocks in 2 Clocks Write the last command(program or erase) to the device in LPC mode. ...
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... Read Start Cycle 0000b LAD[3:0] 010Xb A[31:28] 1 Clock 1 Clock All the address loaded should be within the top 4MByte,FFFFFFFF to FFC00000, or within the bottom 1MByte, 000FFFFF to 000E0000. Preliminary W49V002A Address A[27:24] A[23:20] A[19:16] A[15:12] A[7:4] A[3:0] A[11:8] Load Address "An" Clocks Write the last command(program or erase) to the device in LPC mode. ...
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... Start LAD[3:0] 0000b 011Xb A[31:28] A[27:24] A[23:20] A[19:16] 1 Clock 1 Clock All the address loaded should be within the top 4MByte,FFFFFFFF to FFC00000, or within the bottom 1MByte, 000FFFFF to 000E0000. Preliminary W49V002A Address A[31:28] A[27:24] A[23:20] A[19:16] 0101b 0101b 0101b X101b Load Address "5555" Clocks Write the 1st command to the device in LPC mode. ...
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... Memory Write Cycle 6th Start LAD[3:0] 0000b 011Xb 1 Clock 1 Clock All the address loaded should be within the top 4MByte,FFFFFFFF to FFC00000, or within the bottom 1MByte, 000FFFFF to 000E0000. Preliminary W49V002A Address A[31:28] A[27:24] A[23:20] A[19:16] X101b 0101b 0101b 0101b Load Data "AA" Load Address "5555" Clocks in 2 Clocks Write the 1st command to the device in LPC mode ...
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... Write 6th Start Cycle LAD[3:0] 0000b 011Xb 1 Clock 1 Clock All the address loaded should be within the top 4MByte,FFFFFFFF to FFC00000, or within the bottom 1MByte, 000FFFFF to 000E0000. Preliminary W49V002A Address A[31:28] A[27:24] A[23:20] A[19:16] 0101b 0101b 0101b X101b Load Data "AA" Load Address "5555" Clocks Write the 1st command to the device in LPC mode ...
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... LAD[3:0] 010Xb 1 Clock 1 Clock Note: Read the DQ[4:0] to capture the states(High or Low) of the GPI[4:0] input pins. The DQ[7:5] are reserved pins. Reset Timing Diagram VDD CLK #RESET LAD[3:0] #LFRAM Preliminary W49V002A Address A[23:20] A[19:16] 0000b 0001b 0000b 0000b Load Address "FFBC0100(hex)" Clocks T PRST T ...
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... Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. Preliminary W49V002A POWER SUPPLY STANDBY VDD CURRENT MAX. ...
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... Seating Plane G E 32L STSOP(8 x 14mm £ Preliminary W49V002A Symbol Notes: 1. Dimensions D & not include interlead flash Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches 4. General appearance spec. should be based on final A ...
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... TEL: 886 -2-27190505 TEL: 886 -2-27190505 FAX: 886-2-27197502 FAX: 886-2-27197502 Note: All data and specifications are subject to change withou t notice. Note: All data and specifications are subject to change withou t notice. Preliminary W49V002A PAGE - Initial Issued Winbond Electronics (H.K.) Ltd. Winbond Electronics (H.K.) Ltd. ...