k9f5608u0b-yib0 Samsung Semiconductor, Inc., k9f5608u0b-yib0 Datasheet
k9f5608u0b-yib0
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k9f5608u0b-yib0 Summary of contents
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... K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0 Document Title 32M x 8 Bit , 16M x 16 Bit NAND Flash Memory Revision History Revision No. History 0.0 Initial issue. 0.1 At Read2 operation in X16 device : are Don’t care ==> 0 (R/B) of 1.8V device is changed. OL -min. Value: 7mA -->3mA -typ. Value: 8mA -->4mA 2. AC parameter is changed. tRP(min.) : 30ns --> ...
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... The min. Vcc value 1.8V devices is changed. K9F56XXQ0B : Vcc 1.65V~1.95V --> 1.70V~1.95V 0.7 Pb-free Package is added. K9F5608U0B-FCB0,FIB0 K9F5608Q0B-HCB0,HIB0 K9F5616U0B-HCB0,HIB0 K9F5616U0B-PCB0,PIB0 K9F5616Q0B-HCB0,HIB0 K9F5608U0B-HCB0,HIB0 K9F5608U0B-PCB0,PIB0 0.8 New definition of the number of invalid blocks is added. (Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb memory space.) Pin assignment of TBGA A3 ball is changed. 0.9 (before) N.C --> ...
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... Pin WSOP I (12X17X0.7mm) - K9F56XXU0B-PCB0/PIB0 48 - Pin TSOP I ( 0.5 mm pitch) - Pb-free Package - K9F56XXX0B-HCB0/HIB0 63- Ball TBGA ( /0.8mm pitch , Width 1.0 mm) - Pb-free Package - K9F5608U0B-FCB0/FIB0 48 - Pin WSOP I (12X17X0.7mm) - Pb-free Package * K9F5608U0B-V,F(WSOPI ) is the same device as K9F5608U0B-Y,P(TSOP1) except package type. 3 FLASH MEMORY PKG Type TBGA TSOP1 TBGA ...
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... K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0 PIN CONFIGURATION (TSOP1) K9F56XXU0B-YCB0,PCB0/YIB0,PIB0 X16 X8 N.C N.C 1 N.C N.C 2 N.C N.C 3 N.C N.C 4 N.C N.C 5 GND GND 6 R/B R N.C N.C 10 N.C N.C 11 Vcc Vcc 12 Vss Vss 13 N.C N.C 14 N.C N.C 15 CLE CLE 16 ALE ALE N.C N.C 20 N.C N.C 21 N.C N.C 22 N.C N.C 23 N.C N.C 24 PACKAGE DIMENSIONS 48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I) ...
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... K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0 PIN CONFIGURATION (TBGA) K9F56XXX0B-DCB0,HCB0/DIB0,HIB0 X8 DNU DNU DNU /WP ALE Vss /CE /WE NC /RE CLE I/ I/O1 NC VccQ I/O5 I/O7 Vss I/O2 I/O3 I/O4 I/O6 DNU DNU DNU DNU (Top View) PACKAGE DIMENSIONS 63-Ball TBGA (measured in millimeters) Top View 9 ...
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... K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0 PIN CONFIGURATION (WSOP1) K9F5608U0B-VCB0,FCB0/VIB0,FIB0 N.C 1 N.C 2 DNU 3 N.C 4 N.C 5 N DNU 10 N.C 11 Vcc 12 Vss 13 N.C 14 DNU 15 CLE 16 ALE N.C 20 N.C 21 DNU 22 N.C 23 N.C 24 PACKAGE DIMENSIONS 48-PIN LEAD/LEAD FREE PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE ( WSOP1 - 1217F ...
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... K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0 PIN DESCRIPTION Pin Name DATA INPUTS/OUTPUTS I/O ~ I/O The I/O pins are used to input command, address and data, and to output data during read operations. The 0 7 (K9F5608X0B) I/O pins float to high-z when the chip is deselected or when the outputs are disabled. I/O ~ I/O I/O8 ~ I/O15 are used only in X16 organization device. Since command input and address input are x8 oper- ...
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... K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0 Figure 1-1. K9F5608X0B (X8) FUNCTIONAL BLOCK DIAGRAM X-Buffers Latches & Decoders Y-Buffers Latches & Decoders Command Command Register CE Control Logic RE & High Voltage WE Generator CLE ALE Figure 2-1. K9F5608X0B (X8) ARRAY ORGANIZATION 64K Pages 1st half Page Register ...
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... K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0 Figure 1-2. K9F5616X0B (X16) FUNCTIONAL BLOCK DIAGRAM X-Buffers Latches & Decoders Y-Buffers Latches & Decoders Command Command Register CE Control Logic RE & High Voltage WE Generator CLE ALE Figure 2-2. K9F5616X0B (X16) ARRAY ORGANIZATION 64K Pages ...
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... K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0 PRODUCT INTRODUCTION The K9F56XXX0B is a 264Mbit(276,824,064 bit) memory organized as 65,536 rows(pages) by 528(X8 device) or 264(X16 device) columns. Spare eight columns are located from column address of 512~527(X8 device) or 256~263(X16 device). A 528-byte(X8 device) or 264-word(X16 device) data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations ...
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... K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0 ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative K9F56XXX0B-XCB0 Temperature Under Bias K9F56XXX0B-XIB0 K9F56XXX0B-XCB0 Storage Temperature K9F56XXX0B-XIB0 Short Circuit Current NOTE: 1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins ...
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... X X Read Mode Write Mode Data Input L X Data Output L X During Read(Busy) on K9F5608U0B_Y,P or K9F5608U0B_V,F During Read(Busy) on the devices except K9F5608U0B_Y,P and L X K9F5608U0B_V During Program(Busy During Erase(Busy Write Protect 0V 0V/V (2) Stand-by CC Symbol Min ...
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... Output Hi Low WE High to RE Low Device Resetting Time (Read/Program/Erase) Last RE High to Busy(at sequential read) K9F5608U0B- CE High to Ready(in case of interception read) Y,P,V,F only CE High Hold Time(at the last serial read) NOTE : 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us. ...
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... K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0 NAND Flash Technical Notes Invalid Block(s) Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The infor- mation regarding the invalid block( called as the invalid block information. Devices with invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics ...
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... K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0 NAND Flash Technical Notes (Continued) Error in write or read operation Within its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail- ure after erase or program, block replacement should be done ...
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... K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0 NAND Flash Technical Notes (Continued) Erase Flow Chart Start Write 60h Write Block Address Write D0h Read Status Register I R Yes * No Erase Error I Yes Erase Completed : If erase operation results in an error, map out * the failing block and replace it with another block. ...
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... K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0 Pointer Operation of K9F5608X0B(X8) Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’00h’ command sets the pointer to ’A’ area(0~255byte), ’01h’ command sets the pointer to ’B’ area(256~511byte), and ’50h’ command sets the pointer to ’ ...
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... K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0 Pointer Operation of K9F5616X0B(X16) Samsung NAND Flash has two address pointer commands as a substitute for the most significant column address. ’00h’ command sets the pointer to ’A’ area(0~255word), and ’50h’ command sets the pointer to ’B’ area(256~263word). With these commands, the starting column address can be set to any of a whole page(0~263word). ’ ...
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... Figure 7. Read Operation with CE don’t-care. CLE CE RE ALE R/B WE I/Ox 00h Start Add.(3Cycle) K9F5616Q0B-DCB0,DIB0,HCB0,HIB0 K9F5616U0B-YCB0,YIB0,PCB0,PIB0 K9F5616U0B-DCB0,DIB0,HCB0,HIB0 CE don’t-care Data Input I K9F5608U0B_Y,P or K9F5608U0B_V,F CE must be held low during FLASH MEMORY Data Input 10h t CEA t REA out CE don’t-care Data Output(sequential) ...
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... K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0 Device K9F5608X0B(X8 device) K9F5616X0B(X16 device) NOTE: 1. I/O8~15 must be set to "0" during command or address input. 2. I/O8~15 are used only for data bus. * Command Latch Cycle CLE t CLS ALS ALE I/Ox * Address Latch Cycle t CLS CLE ALS ...
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... K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0 * Input Data Latch Cycle CLE ALS WC ALE I/Ox DIN 0 * Serial access Cycle after Read I/ R/B NOTES : Transition is measured 200mV from steady state voltage with load. This parameter is sampled and not 100% tested. K9F5616Q0B-DCB0,DIB0,HCB0,HIB0 K9F5616U0B-YCB0,YIB0,PCB0,PIB0 ...
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... On K9F5608U0B_Y,P or K9F5608U0B_V,F CE must be held low during A17~A24 Dout N Dout N+1 Dout N+2 Busy NOTES : 1) is only valid 22 FLASH MEMORY t CHZ RHZ t REA t OH Status Output 1) t CEH t CHZ CRY t RHZ t OH Dout N+3 Dout K9F5608U0B_Y,P or K9F5608U0B_V,F ...
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... On K9F5608U0B_Y,P or K9F5608U0B_V,F CE must be held low during Dout N+1 Dout N Row Add2 Page(Row) Address Busy On K9F5608U0B_Y,P or K9F5608U0B_V,F CE must be held low during Row Add1 Row Add2 ~A are Valid Address & are Don care ...
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... WC WE ALE RE N Address I/Ox 80h Col. Add Row Add1 Sequential Data Column Page(Row) Input Command Address Address R/B K9F5616Q0B-DCB0,DIB0,HCB0,HIB0 K9F5616U0B-YCB0,YIB0,PCB0,PIB0 K9F5616U0B-DCB0,DIB0,HCB0,HIB0 (only for K9F5608U0B-Y,P and K9F5608U0B-V,F, Valid with in a block) Dout Dout Dout Row Add2 N N+1 N+2 Ready Busy M+1 N Output Din Din ...
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... K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0 COPY-BACK PROGRAM OPERATION CLE ALE RE I/Ox 00h Col. Add Row Add1 Row Add2 Column Page(Row) Address Address R/B BLOCK ERASE OPERATION CLE ALE RE I/Ox 60h A9~A16 A17~A24 Page(Row) Address R/B Auto Block Erase Setup Command K9F5616Q0B-DCB0,DIB0,HCB0,HIB0 K9F5616U0B-YCB0,YIB0,PCB0,PIB0 ...
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... K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0 MANUFACTURE & DEVICE ID READ OPERATION CLE CE WE ALE RE I/Ox 90h Read ID Command Address. 1cycle K9F5616Q0B-DCB0,DIB0,HCB0,HIB0 K9F5616U0B-YCB0,YIB0,PCB0,PIB0 K9F5616U0B-DCB0,DIB0,HCB0,HIB0 REA 00h ECh Maker Code Device K9F5608Q0B K9F5608U0B K9F5616Q0B K9F5616U0B 26 FLASH MEMORY Device Code* Device Code Device Code* 35h 75h XX45h XX55h ...
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... Figures 8, 9 show typical sequence and timings for each read operation. Sequential Row Read is available only for K9F5608U0B_Y,P and K9F5608U0B_V,F : After the data of last column address is clocked out, the next page is automatically selected for sequential row read. Waiting 10 s again allows reading the selected page. The sequential row read operation is terminated by bringing CE high. Unless the operation is aborted, the page address is automatically incremented for sequential row read as in Read1 operation and spare sixteen bytes of each page may be sequentially read ...
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... A & device : Don’t care 4 7 X16 device : are "L" Figure 8-1. Sequential Row Read1 Operation (only for K9F5608U0B-Y,P and K9F5608U0B-V,F Valid with in a block ) R/B I/Ox 00h Start Add.(3Cycle) 01h & ...
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... K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0 Figure 9-1. Sequential Row Read2 Operation (GND Input=Fixed Low) (only for K9F5608U0B-Y,P and K9F5608U0B-V,F Valid with in a block) R/B I/Ox Start Add.(3Cycle) 50h & Don t Care) K9F5616Q0B-DCB0,DIB0,HCB0,HIB0 K9F5616U0B-YCB0,YIB0,PCB0,PIB0 K9F5616U0B-DCB0,DIB0,HCB0,HIB0 Data Output Data Output ...
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... K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0 PAGE PROGRAM The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte/word or consecutive bytes/words up to 528 264 (X8 device) or (X16 device) ming operation within the same page without an intervening erase operation should not exceed 2 for main array and 3 for spare array ...
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... K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0 BLOCK ERASE The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase Setup com- mand(60h). Only address valid while address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions ...
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... Table5. Device Status Operation Mode K9F5616Q0B-DCB0,DIB0,HCB0,HIB0 K9F5616U0B-YCB0,YIB0,PCB0,PIB0 K9F5616U0B-DCB0,DIB0,HCB0,HIB0 t CEA WHR REA ECh 00h Maker code Device K9F5608Q0B K9F5608U0B K9F5616Q0B K9F5616U0B t RST After Power-up Read 1 32 FLASH MEMORY Device Code* Device code Device Code* 35h 75h 45h 55h After Reset ...
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... K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0 READY/BUSY The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command reg- ister or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied ...
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... K9F5608U0B-VCB0,VIB0,FCB0,FIB0 K9F5608Q0B-DCB0,DIB0,HCB0,HIB0 K9F5608U0B-YCB0,YIB0,PCB0,PIB0 K9F5608U0B-DCB0,DIB0,HCB0,HIB0 Data Protection & Powerup sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 1.3V. WP pin provides hardware protection and is recommended to be kept at V during power-up and power-down and recovery time of minimum required before internal circuit gets ready for any com- IL mand sequences as shown in Figure 16 ...