k9f5608u0c Samsung Semiconductor, Inc., k9f5608u0c Datasheet
k9f5608u0c
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k9f5608u0c Summary of contents
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... The min. Vcc value 1.8V devices is changed. K9F56XXQ0C : Vcc 1.65V~1.95V --> 1.70V~1.95V 2.2 Pb-free Package is added. K9F5608U0C-FCB0,FIB0 K9F5608Q0C-HCB0,HIB0 K9F5616U0C-HCB0,HIB0 K9F5616U0C-PCB0,PIB0 K9F5616Q0C-HCB0,HIB0 K9F5608U0C-HCB0,HIB0 K9F5608U0C-PCB0,PIB0 2.3 Errata is added.(Front Page)-K9F56XXQ0C tWC tWH tWP tRC tREH tRP tREA tCEA Specification 45 Relaxed value 60 New definition of the number of invalid blocks is added. 2.4 ...
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... K9F5608Q0C K9F5616Q0C K9F5608D0C K9F5616D0C K9F5608U0C K9F5616U0C Document Title 32M x 8 Bit , 16M x 16 Bit NAND Flash Memory Revision History Revision No. History 2.6 1. tREA value of 1.8V device is changed. K9F56XXQ0C : tREA 30ns --> 35ns 2. Errata is deleted. Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site. ...
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... Pin WSOP I (12X17X0.7mm) - K9F56XXX0C-PCB0/PIB0 48 - Pin TSOP I ( 0.5 mm pitch)- Pb-free Package - K9F56XXX0C-HCB0/HIB0 63- Ball TBGA ( /0.8mm pitch , Width 1.0 mm) - Pb-free Package - K9F5608U0C-FCB0/FIB0 48 - Pin WSOP I (12X17X0.7mm)- Pb-free Package * K9F5608U0C-V,F(WSOPI ) is the same device as K9F5608U0C-Y,P(TSOP1) except package type. 3 FLASH MEMORY PKG Type TBGA TSOP1 TBGA ...
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... K9F5608Q0C K9F5616Q0C K9F5608D0C K9F5616D0C K9F5608U0C K9F5616U0C PIN CONFIGURATION (TSOP1) K9F56XXU0C-YCB0,PCB0/YIB0,PIB0 X16 X8 N.C N.C 1 N.C N.C 2 N.C N.C 3 N.C N.C 4 N.C N.C 5 N.C N.C 6 R/B R N.C N.C 10 N.C N.C 11 Vcc Vcc 12 Vss Vss 13 N.C N.C 14 N.C N.C 15 CLE CLE 16 ALE ALE N.C N.C 20 N.C N.C 21 N.C N.C 22 N.C N.C 23 N.C N.C 24 PACKAGE DIMENSIONS 48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I) ...
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... K9F5608Q0C K9F5616Q0C K9F5608D0C K9F5616D0C K9F5608U0C K9F5616U0C PIN CONFIGURATION (TBGA N.C N.C N.C A /WP ALE Vss / /RE CLE I/ I/O1 NC VccQ I/O5 H Vss I/O2 I/O3 I/O4 N.C N.C Top View N.C N.C PACKAGE DIMENSIONS 63-Ball TBGA (measured in millimeters) Top View 9.00 0.10 #A1 K9F56XXX0C-DCB0,HCB0/DIB0,HIB0 ...
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... K9F5608Q0C K9F5616Q0C K9F5608D0C K9F5616D0C K9F5608U0C K9F5616U0C PIN CONFIGURATION (WSOP1) K9F5608U0C-VCB0,FCB0/VIB0,FIB0 N.C 1 N.C 2 DNU 3 N.C 4 N.C 5 N DNU 10 N.C 11 Vcc 12 Vss 13 N.C 14 DNU 15 CLE 16 ALE N.C 20 N.C 21 DNU 22 N.C 23 N.C 24 PACKAGE DIMENSIONS 48-PIN LEAD/LEAD FREE PLASTIC VERY VERY THIN SMALL OUT-LINE PACKAGE TYPE (I) ...
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... K9F5608Q0C K9F5616Q0C K9F5608D0C K9F5616D0C K9F5608U0C K9F5616U0C PIN DESCRIPTION Pin NAME DATA INPUTS/OUTPUTS I/O ~ I/O The I/O pins are used to input command, address and data, and to output data during read operations. The 0 7 (K9F5608X0C) I/O pins float to high-z when the chip is deselected or when the outputs are disabled. ...
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... K9F5608Q0C K9F5616Q0C K9F5608D0C K9F5616D0C K9F5608U0C K9F5616U0C Figure 1-1. K9F5608X0C (X8) FUNCTIONAL BLOCK DIAGRAM X-Buffers Latches & Decoders Y-Buffers Latches & Decoders Command Command Register CE Control Logic RE & High Voltage WE Generator CLE ALE Figure 2-1. K9F5608X0C (X8) ARRAY ORGANIZATION 64K Pages ...
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... K9F5608Q0C K9F5616Q0C K9F5608D0C K9F5616D0C K9F5608U0C K9F5616U0C Figure 1-2. K9F5616X0C (X16) FUNCTIONAL BLOCK DIAGRAM X-Buffers Latches & Decoders Y-Buffers Latches & Decoders Command Command Register CE Control Logic RE & High Voltage WE Generator CLE ALE Figure 2-2. K9F5616X0C (X16) ARRAY ORGANIZATION ...
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... K9F5608Q0C K9F5616Q0C K9F5608D0C K9F5616D0C K9F5608U0C K9F5616U0C PRODUCT INTRODUCTION The K9F56XXX0C is a 264Mbit(276,824,064 bit) memory organized as 65,536 rows(pages) by 528(X8 device) or 264(X16 device) columns. Spare eight columns are located from column address of 512~527(X8 device) or 256~263(X16 device). device) or 264-word(X16 device) data register is connected to memory cell arrays accommodating data transfer between the I/O buff- ers and memory during page read and page program operations ...
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... K9F5608Q0C K9F5616Q0C K9F5608D0C K9F5616D0C K9F5608U0C K9F5616U0C ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative K9F56XXX0C-XCB0 Temperature Under Bias K9F56XXX0C-XIB0 K9F56XXX0C-XCB0 Storage Temperature K9F56XXX0C-XIB0 Short Circuit Current NOTE : 1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. ...
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... K9F5608Q0C K9F5616Q0C K9F5608D0C K9F5616D0C K9F5608U0C K9F5616U0C DC AND OPERATING CHARACTERISTICS Parameter Symbol Test Conditions tRC=50ns, CE=V Sequential Read Operating I =0mA OUT Current Program Erase Stand-by Current(TTL CE=V SB Stand-by Current(CMOS CE=V SB Input Leakage Current Vcc(max Output Leakage Current ...
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... PRE Read Mode Write Mode Data Input X X Data Output X X During Read(Busy) on K9F5608U0C_Y,P or K9F5608U0C_V,F During Read(Busy) on the devices except K9F5608U0C_Y,P and X X K9F5608U0C_V During Program(Busy During Erase(Busy Write Protect 0V/V (2) 0V/V (2) Stand- ...
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... WE High to RE Low in Block Lcok Mode Device Resetting Time (Read/Program/Erase) Last RE High to Busy(at sequential read) K9F5608U0C- CE High to Ready(in case of interception read) Y,V,P,F only CE High Hold Time(at the last serial read) NOTE : 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us. ...
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... K9F5608Q0C K9F5616Q0C K9F5608D0C K9F5616D0C K9F5608U0C K9F5616U0C NAND Flash Technical Notes Invalid Block(s) Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The infor- mation regarding the invalid block( called as the invalid block information. Devices with invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics ...
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... K9F5608Q0C K9F5616Q0C K9F5608D0C K9F5616D0C K9F5608U0C K9F5616U0C NAND Flash Technical Notes Error in write or read operation Within its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail- ure after erase or program, block replacement should be done ...
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... K9F5608Q0C K9F5616Q0C K9F5608D0C K9F5616D0C K9F5608U0C K9F5616U0C NAND Flash Technical Notes Erase Flow Chart Start Write 60h Write Block Address Write D0h Read Status Register I R Yes * No Erase Error I Yes Erase Completed : If erase operation results in an error, map out * the failing block and replace it with another block. ...
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... K9F5608Q0C K9F5616Q0C K9F5608D0C K9F5616D0C K9F5608U0C K9F5616U0C Pointer Operation of K9F5608X0C(X8) Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’00h’ command sets the pointer to ’A’ area(0~255byte), ’01h’ command sets the pointer to ’B’ area(256~511byte), and ’50h’ command sets the pointer to ’ ...
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... K9F5608Q0C K9F5616Q0C K9F5608D0C K9F5616D0C K9F5608U0C K9F5616U0C Pointer Operation of K9F5616X0C(X16) Samsung NAND Flash has two address pointer commands as a substitute for the most significant column address. ’00h’ command sets the pointer to ’A’ area(0~255word), and ’50h’ command sets the pointer to ’B’ area(256~263word). With these commands, the starting column address can be set to any of a whole page(0~263word). ’ ...
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... Figure 7. Read Operation with CE don’t-care. CLE CE RE ALE R/B WE I/Ox 00h Start Add.(3Cycle) CE don’t-care Data Input I K9F5608U0C_Y,P or K9F5608U0C_V,F CE must be held low during FLASH MEMORY Data Input 10h t CEA t REA t OH out CE don’t-care Data Output(sequential) ...
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... K9F5608Q0C K9F5616Q0C K9F5608D0C K9F5616D0C K9F5608U0C K9F5616U0C Device K9F5608X0C(X8 device) K9F5616X0C(X16 device) NOTE: 1. I/O8~15 must be set to "0" during command or address input. I/O8~15 are used only for data bus. Command Latch Cycle CLE t CLS ALS ALE I/Ox Address Latch Cycle t CLS CLE t CS ...
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... K9F5608Q0C K9F5616Q0C K9F5608D0C K9F5616D0C K9F5608U0C K9F5616U0C Input Data Latch Cycle CLE ALS WC ALE I/Ox DIN 0 Sequential Out Cycle after Read I/ R/B NOTES : Transition is measured 200mV from steady state voltage with load. This parameter is sampled and not 100% tested. ...
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... A17~A24 Dout N Dout N+1 Page(Row) Address Busy NOTES : 1) is only valid 23 FLASH MEMORY t t CEA CHZ RHZ t REA t OH Status Output 1) t CEH t CHZ RHZ t OH Dout N+2 Dout N+3 Dout K9F5608U0C_Y,P or K9F5608U0C_V,F CRY ...
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... On K9F5608U0C_Y,P or K9F5608U0C_V,F CE must be held low during Dout N+1 Dout N Row Add2 Page(Row) Address Busy On K9F5608U0C_Y,P or K9F5608U0C_V,F CE must be held low during Row Add1 Row Add2 ~A are Valid Address & are Don care ...
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... PAGE PROGRAM OPERATION CLE ALE RE N Address I/Ox 80h Col. Add Row Add1 Sequential Data Column Page(Row) Input Command Address Address R/B (only for K9F5608U0C-Y,P or K9F5608U0C-V,F) Dout Dout Dout Row Add2 N N+1 N+2 Ready Busy M+1 N Output Din Din Din Row Add2 ...
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... K9F5608Q0C K9F5616Q0C K9F5608D0C K9F5616D0C K9F5608U0C K9F5616U0C COPY-BACK PROGRAM OPERATION CLE ALE RE I/Ox 00h Col. Add Row Add1 Row Add2 Column Page(Row) Address Address R/B BLOCK ERASE OPERATION CLE ALE RE I/Ox 60h A9~A16 A17~A24 Page(Row) Address R/B Auto Block Erase Setup Command ...
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... K9F5616U0C MANUFACTURE & DEVICE ID READ OPERATION CLE CE WE ALE RE I/Ox 90h Read ID Command Address. 1cycle REA 00h ECh Maker Code Device K9F5608Q0C K9F5608D0C K9F5608U0C K9F5616Q0C K9F5616D0C K9F5616U0C 27 FLASH MEMORY Device Code* Device Code Device Code* 35h 75h 75h XX45h XX55h XX55h ...
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... Figures 8,9 show typical sequence and timings for each read operation. Sequential Row Read is available only on K9F5608U0C_Y,P or K9F5608U0C_V,F : After the data of last column address is clocked out, the next page is automatically selected for sequential row read. Waiting 10 s again allows reading the selected page. The sequential row read operation is terminated by bringing CE high. Unless the operation is aborted, the page address is automatically incremented for sequential row read as in Read1 operation and spare sixteen bytes of each page may be sequentially read ...
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... Data Field On K9F5608U0C_Y,P or K9F5608U0C_V,F CE must be held low during Main array Data Field Spare Field (only for K9F5608U0C-Y,P or K9F5608U0C-V, Data Output Data Output 1st (528 Byte) (01h Command) 2nd half array 1st half array 1st 2nd Nth ...
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... K9F5616U0C Figure 9-1. Sequential Row Read2 Operation R/B I/Ox Start Add.(3Cycle) 50h & Don t Care) (only for K9F5608U0C-Y,P or K9F5608U0C-V, Data Output Data Output 1st 24 1st Block Nth Data Field Spare Field 30 FLASH MEMORY t R Data Output ...
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... K9F5608Q0C K9F5616Q0C K9F5608D0C K9F5616D0C K9F5608U0C K9F5616U0C PAGE PROGRAM The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte/word or consecutive bytes/words up to 528 264 (X8 device) or (X16 device) ming operation within the same page without an intervening erase operation should not exceed 2 for main array and 3 for spare array. ...
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... K9F5608Q0C K9F5616Q0C K9F5608D0C K9F5616D0C K9F5608U0C K9F5616U0C BLOCK ERASE The Erase operation is done on a block basis. Block address loading is accomplished in two cycles initiated by an Erase Setup com- mand(60h). Only address valid while loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions ...
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... R/B I/Ox FFh Table5. Device Status Operation Mode t CEA WHR1 REA ECh 00h Maker code Device K9F5608Q0C K9F5608D0C K9F5608U0C K9F5616Q0C K9F5616D0C K9F5616U0C t RST After Power-up Read 1 33 FLASH MEMORY Device Code* Device code Device Code* 35h 75h 75h XX45h XX55h XX55h ...
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... K9F5608Q0C K9F5616Q0C K9F5608D0C K9F5616D0C K9F5608U0C K9F5616U0C > In high state of LOCKPRE pin, Block lock mode and Power on Auto read are enabled, otherwise it is regarded as NAND Flash without LOCKPRE pin. Block Lock Mode Block Lock mode is enabled while LOCKPRE pin state is high, which is to offer protection features for NAND Flash data. The Block Lock mode is divided into Unlock, Lock, Lock-tight operation ...
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... K9F5608Q0C K9F5616Q0C K9F5608D0C K9F5616D0C K9F5608U0C K9F5616U0C 2) Unlock - Command Sequence: Unlock block Command(23h) + Start block address + Command(24h) + End block address - Unlocked blocks can be programmed or erased unlocked block’s status can be changed to the locked or lock-tighten state using the appropriate commands. - Only one consecutive area can be released to unlock state from lock state; Unlocking multi area is not available. ...
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... K9F5608Q0C K9F5616Q0C K9F5608D0C K9F5616D0C K9F5608U0C K9F5616U0C WPx = H & Unlock block Command (23h) + Start Block Address unlock Block Lock reset WPx = H & WPx = L (>100ns) Lock block command (2Ah) WPx = H & Lock-tight block command (2Ch) Lock-tight Figure 15. State diagram of Block Lock Program/Erase OPERATION(In Locked or Lock-tighten Block) ...
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... K9F5608Q0C K9F5616Q0C K9F5608D0C K9F5616D0C K9F5608U0C K9F5616U0C 2. Block Lock Status Read Block Lock Status can be read on a block basis, which may be read to find out whether designated block is available to be pro- grammed or erased. After writing 7Ah command to the command register. and block address to be checked, a read cycle outputs the content of the Block Lock Status Register to the I/O pins on the falling edge RE, whichever occurs last ...
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... K9F5608Q0C K9F5616Q0C K9F5608D0C K9F5616D0C K9F5608U0C K9F5616U0C Power-On Auto-Read The device is designed to offer automatic reading of the first page without command and address input sequence during power-on. An internal voltage detector enables auto-page read functions when Vcc reaches about 1.8V. LOCKPRE pin controls activation of auto- page read function. Auto-page read function is enabled only when LOCKPRE pin is logic high state after power-on without latency ...
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... K9F5608Q0C K9F5616Q0C K9F5608D0C K9F5616D0C K9F5608U0C K9F5616U0C READY/BUSY The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command reg- ister or random read is started after address loading ...
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... K9F5608Q0C K9F5616Q0C K9F5608D0C K9F5616D0C K9F5608U0C K9F5616U0C 300n 200n 100n 300n 200n 100n 300n 200n 100n Rp value guidance V (Max Rp(min, 1.8V part (Max Rp(min, 2.65V part (Max Rp(min, 3.3V part) = where I is the sum of the input currents of all devices tied to the R/B pin. ...
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... K9F5608Q0C K9F5616Q0C K9F5608D0C K9F5616D0C K9F5608U0C K9F5616U0C Data Protection & Power up sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 1.1V(1.8V device), 1.8V(2.65V device), 2V(3.3V device). WP pin provides hard- ware protection and is recommended to be kept at V required before internal circuit gets ready for any command sequences as shown in Figure 18 ...