k9f5608u0m-yib0 Samsung Semiconductor, Inc., k9f5608u0m-yib0 Datasheet

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... Initial issue. 0.1 Revised real-time map-out algorithm(refer to technical notes) 0.2 1. Changed device name i. KM29U256T -> K9F5608U0M-YCB0 ii. KM29U256IT -> K9F5608U0M-YIB0 0.3 1. Changed tWP AC Timing - If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise tWP may be minimum 25ns. 2. Changed Sequential Row Read operation - The Sequential Read 1 and 2 operation is allowed only within a block 3 ...

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... K9F5608U0M-YCB0,K9F5608U0M-YIB0 32M x 8 Bit NAND Flash Memory FEATURES Voltage Supply : 2.7V~3.6V Organization - Memory Cell Array : (32M + 1024K)bit x 8bit - Data Register : (512 + 16)bit x8bit Automatic Program and Erase - Page Program : (512 + 16)Byte - Block Erase : (16K + 512)Byte 528-Byte Page Read Operation - Random Access : 10 s(Max.) - Serial Page Access : 50ns(Min ...

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... K9F5608U0M-YCB0,K9F5608U0M-YIB0 Figure 1. FUNCTIONAL BLOCK DIAGRAM X-Buffers Latches & Decoders Y-Buffers Latches & Decoders Command Command CE Control Logic RE & High Voltage WE Generator CLE ALE Figure 2. ARRAY ORGANIZATION 64K Pages 1st half Page Register (=2,048 Blocks) (=256 Bytes) ...

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... K9F5608U0M-YCB0,K9F5608U0M-YIB0 PRODUCT INTRODUCTION The K9F5608U0M is a 264Mbit(276,824,064 bit) memory organized as 65,536 rows(pages) by 528 columns. Spare sixteen columns are located from column address of 512 to 527. A 528-byte data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made cells that are serially connected to form a NAND structure ...

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... K9F5608U0M-YCB0,K9F5608U0M-YIB0 PIN DESCRIPTION Command Latch Enable(CLE) The CLE input controls the activating path for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE signal. Address Latch Enable(ALE) The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of WE with ALE high ...

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... Input Low Voltage, All inputs Output High Voltage Level Output Low Voltage Level Output Low Current(R/B) Symbol BIAS T STG +0.3V which, during transitions, may overshoot K9F5608U0M-YIB0 A Symbol Min V 2 (Recommended operating conditions otherwise noted.) Symbol Test Conditions I 1 tRC=50ns, CE ...

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... Invalid blocks are defined as blocks that contain one or more bad bits to access these invalid blocks for program and erase. 2. The 1st block, which is placed on 00h block address, is guaranteed valid block AC TEST CONDITION (K9F5608U0M-YCB0 :TA K9F5608U0M-YIB0:TA=- VCC=2.7V~3.6V unless otherwise) Parameter Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load (3 ...

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... K9F5608U0M-YCB0,K9F5608U0M-YIB0 AC Timing Characteristics for Command / Address / Data Input Parameter CLE Set-up Time CLE Hold Time CE Setup Time CE Hold Time WE Pulse Width ALE Setup Time ALE Hold Time Data Setup Time Data Hold Time Write Cycle Time WE High Hold Time NOTE : 1. If tCS is set less than 10ns, tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns. ...

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... K9F5608U0M-YCB0,K9F5608U0M-YIB0 NAND Flash Technical Notes Invalid Block(s) Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The infor- mation regarding the invalid block( called as the invalid block information. Devices with invalid block(s) have the same quality level or as devices with all valid blocks and have the same AC and DC characteristics ...

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... K9F5608U0M-YCB0,K9F5608U0M-YIB0 NAND Flash Technical Notes (Continued) Error in write or read operation Over its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail- ure after erase or program, block replacement should be done ...

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... K9F5608U0M-YCB0,K9F5608U0M-YIB0 NAND Flash Technical Notes (Continued) Erase Flow Chart Start Write 60h Write Block Address Write D0h Read Status Register I R Erase Error I Erase Completed : If erase operation results in an error, map out * the failing block and replace it with another block. ...

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... K9F5608U0M-YCB0,K9F5608U0M-YIB0 Pointer Operation of K9F5608U0M Samsung NAND Flash has three address pointer commands as a substitute for the two most significant column addresses. ’ 00h’ command sets the pointer to ’ A’ area(0~255byte), ’ 01h’ command sets the pointer to ’ B’ area(256~511byte), and ’ 50h’ command sets the pointer to ’ ...

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... K9F5608U0M-YCB0,K9F5608U0M-YIB0 System Interface Using CE don’ t-care. For an easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal 528byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and read- ing would provide significant savings in power consumption ...

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... K9F5608U0M-YCB0,K9F5608U0M-YIB0 * Command Latch Cycle CLE CE WE ALE I Address Latch Cycle CLE CE WE ALE I CLH CLS ALS ALH Command t CLS ALH ALS t ALS ...

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... K9F5608U0M-YCB0,K9F5608U0M-YIB0 * Input Data Latch Cycle CLE CE t ALS ALE I Sequential Out Cycle after Read R/B NOTES : Transition is measured 200mV from steady state voltage with load DIN 0 DIN 1 (CLE=L, WE=H, ALE= ...

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... K9F5608U0M-YCB0,K9F5608U0M-YIB0 * Status Read Cycle CLE I READ1 OPERATION (READ ONE PAGE) CLE ALE RE 00h or 01h I Column Address R/B t CLS t CLS t CLH WHR 70h AR2 Dout N+1 Dout ...

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... K9F5608U0M-YCB0,K9F5608U0M-YIB0 READ1 OPERATION (INTERCEPTED BY CE) CLE CE WE ALE I/O ~ 00h or 01h Column Address R/B READ2 OPERATION (READ ONE PAGE) CLE CE WE ALE RE I/O ~ 50h R/B M Address AR2 Dout Page(Row) Address Busy ...

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... K9F5608U0M-YCB0,K9F5608U0M-YIB0 SEQUENTIAL ROW READ OPERATION CLE CE WE ALE RE 00h I R/B M PAGE PROGRAM OPERATION CLE ALE RE I/O ~ 80h Sequential Data Column Input Command Address R/B (WITHIN A BLOCK) Dout Dout N+1 Ready Busy ...

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... K9F5608U0M-YCB0,K9F5608U0M-YIB0 BLOCK ERASE OPERATION CLE ALE I/O ~ 60h Page(Row) Address R/B Auto Block Erase Setup Command MANUFACTURE & DEVICE ID READ OPERATION CLE CE WE ALE RE 90h I Read ID Command (ERASE ONE BLOCK DOh 17 24 Busy Erase Command ...

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... K9F5608U0M-YCB0,K9F5608U0M-YIB0 DEVICE OPERATION PAGE READ Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command reg- ister along with three address cycles. Once the command is latched, it does not need to be written for the following page read opera- tion ...

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... K9F5608U0M-YCB0,K9F5608U0M-YIB0 Figure 4. Read2 Operation CLE CE WE ALE R/B RE Start Add.(3Cycle) 50h I & Don't Care) Figure 5. Sequential Row Read1 Operation R/B I 00h Start Add.(3Cycle) 01h & (GND input=L, 00h Command) 1st half array ...

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... K9F5608U0M-YCB0,K9F5608U0M-YIB0 Figure 6. Sequential Row Read2 Operation (GND Input=Fixed Low) R/B I/O ~ Start Add.(3Cycle 50h & Don t Care) PAGE PROGRAM The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte or consecutive bytes up to 528 single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation should not exceed 2 for main array and 3 for spare array ...

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... K9F5608U0M-YCB0,K9F5608U0M-YIB0 BLOCK ERASE The Erase operation is done on a block(16K Byte) basis. Block address loading is accomplished in two cycles initiated by an Erase Setup command(60h). Only address A block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. ...

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... K9F5608U0M-YCB0,K9F5608U0M-YIB0 READ ID The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Two read cycles sequentially output the manufacture code(ECh), and the device code (75h) respectively. The command register remains in Read ID mode until further commands are issued to it. Figure 9 shows the operation sequence. ...

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... K9F5608U0M-YCB0,K9F5608U0M-YIB0 READY/BUSY The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command reg- ister or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied ...

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... Package Dimensions PACKAGE DIMENSIONS 48-PIN LEAD PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE( TSOP1 - 1220F #1 #24 ¡Æ 0~8 0.45~0.75 0.018~0.030 20.00 0.20 0.787 0.008 18.40 0.10 0.724 0.004 26 FLASH MEMORY Unit :mm/Inch #48 #25 1.00 0.05 0.039 0.002 0.002 1.20 MAX 0.047 0. 0.020 0.05 MIN ...