s4804 Applied Micro Circuits Corporation (AMCC), s4804 Datasheet

s4804

Manufacturer Part Number

s4804

Description

Oc-48 / 4xoc-12 / 16xoc-3 Sonet/sdh Framer And Pos/atm Mapper

Manufacturer

Applied Micro Circuits Corporation (AMCC)

Datasheet

1.S4804.pdf (2 pages)

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Bonase Electronics (HK) Co., Limited

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s4804CBI41

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TX_SONETCLK_OUT_155_622

RHINE

• Provides a SONET/SDH STS-48/STM-16, 4 STS-12/STM-

• STS-48/STM-16 data stream supports a single STS-48c/

• Each STS-12/STM-4 data stream supports a single STS-

• Each STS-3/STM-1 data stream supports a single

• Supports mixed STS-3 / STS-12 line rates

• Provides full-duplex mapping of ATM cells or packets in

• Supports termination of mixed ATM and POS tributaries.

• Terminates/generates SONET/SDH section, line, and path

• APS port to support protection-switching configurations

• 16-bit, bus interface at 155 MHz for STS-48/STM-16 mode,

• 32-bit, parallel interface (FlexBus-3

• .25 micron, 2.5V core, and 3.3V tolerant I/O.

• Packaged in a 624 Pin CBGA.

OC-48 / 4xOC-12 / 16xOC-3 SONET/SDH FRAMER AND POS/ATM MAPPER

TX_SONETCLK_OUT_155

4, or 16 STS-3/STM-1 line interfaces.

AU-4-16c, or any valid combination of STS-12c/AU-4-4c

and/or STS-3c/AU-4 SONET/SDH payloads.

12c/AU-4-4c or 4 STS-3c/AU-4 SONET/SDH payloads.

STS-3c/AU-4 SONET/SDH payload.

each payload tributary.

layers with transport/section E1, E2, F1, and DCC over-

head interfaces in both transmit and receive directions.

between two RHINE devices.

or serial interfaces operating at 622/155 MHz for STS-12/3

(STM-4/1) modes on the line side.

MHz on the system side.

Features

S4804CBI Block Diagram

RX_SONETCLK[1:16]

TX_SONETCLK_IN

RX_REF_CLK_OUT

RX_LOSEXT[1:16]

TX_DATA[15:0]

RX_DATA[15:0]

TX_FRAME_IN

FRAMER

x16

TOH EXTRACT

) operating at 100

TOH

MON.

SPE/VC

TOH INSERT

GEN.

x16

Proc

Ptr

x16

Intrp

Ptr

GPIO/LED REG

AMCC

x16

POH

MON.

MICROPROCESSOR I/F

x16

TX ATM/HDLC

PROC w/

+ 1)

The S4804 is a highly-integrated VLSI device that provides

full-duplex mapping of packets or ATM cells to SONET/SDH

payloads. It provides support for both uni-directional and

bi-directional rings.

The S4804 provides full section, line, and path overhead

processing, and supports framing, scrambling/descrambling,

alarm signal insertion/detection, and bit-interleaved parity

(B1/B2/B3) processing.

The S4804 is SONET/SDH standards compliant with Bellcore

GR-253, ITU G.707, ITU-T 432.1, ANSI T1.105 -1995, and

IETF RFCs 1619/1661/1662/2615.

A general purpose 8-bit or 16-bit microprocessor interface is

provided for control and monitoring. The interface supports

both Intel

capable of operating in either an interrupt-driven or

polled-mode configuration. In addition, a standard 5 signal

IEEE 1149.1 JTAG Test Port is provided for Boundary Scan

test purposes.

Applications

RX ATM/

CNTRS

HDLC

JTAG PORT

RX ATM/HDLC

+ 1) DeSCRMBL

SCRMBL

PROC w/

•

x16

ATM switches

Packet over SONET Routers and Switches

SONET/SDH Add Drop Multiplexers, Terminal

Multiplexers, and Digital Cross Connects

Test equipment

x16

and Motorola

x16

FIFO

Product Brief Version 2.0 - January 2002

FIFO

x16

PRODUCT BRIEF

type microprocessors, and is

Production Release Information - The information con-

tained in this document is about a product in its fully tested

and characterized phase. All features described herein are

supported. Contact AMCC for updates to this document and

the latest product status.

Part Number - S4804CBI41

RX_CLK_OUT[1:4}

TX_LBYTE[1:0]

TX_SYS_DAT[31:0]

TX_ADR[4:0]

TX_CLAV_PDA[1:4]

TX_CLK_OUT[1:4]

RX_LBYTE[1:0]

RX_EOP[1:4]

TX_ERR[1:4]

TX_EOP[1:4]

TX_PRTY[1:4]

TX_ENB[1:4]

TX_SOC/P[1:4]

RX_ERR[1:4]

TX_CLK[1:4]

RX_SYS_DAT[31:0]

RX_ADR[4:0]

RX_PRTY[1:4]

RX_ENB[1:4]

RX_SOC/P[1:4]

RX_CLAV_PDA[1:4]

RX_CLK[1:4]

RX_DV[1:4]

Related parts for s4804

s4804 Summary of contents

Page 1

... The S4804 is a highly-integrated VLSI device that provides full-duplex mapping of packets or ATM cells to SONET/SDH payloads. It provides support for both uni-directional and bi-directional rings. The S4804 provides full section, line, and path overhead processing, and supports framing, scrambling/descrambling, alarm signal insertion/detection, and bit-interleaved parity (B1/B2/B3) processing. ...

Page 2

... Bit Interleaved Parity (B1/B2/B3) for far-end performance monitoring. On the receive side, the S4804 processes section, line, and path overhead. It performs framing (A1, A2), descrambling, alarm detection, pointer processing, Bit Interleaved Parity monitoring (B1/B2/B3), and error-count accumulation for performance monitoring ...

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