cx28380 Mindspeed Technologies, cx28380 Datasheet
cx28380
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... CX28380 Quad T1/E1 Line Interface The CX28380 is a fully integrated quad line interface unit for both 1.544 Mbps (T1) and 2.048 Mbps (E1) applications designed to complement T1/E1 framers or operate as a stand-alone line interface to synchronous or plesiochronous mappers and multiplexers. The device can be controlled by a serial port in host mode or by hardware mode operation in which device control and status are obtained through non-multiplexed dedicated pins ...
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... Ordering Information Model Number CX28380-16 CX28380G-16* Evaluation Module *The G in the part number indicates that this is an RoHS compliant package. Refer to www.mindspeed.com for additional information. Revision History Revision Level B Final A Preliminary 29380-DSH-001-B Package 128-pin MQFP 128-pin MQFP BT00–D660–001 Date ...
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... Line rate – References as low as 8 kHz ® Mindspeed Technologies Mindspeed Proprietary and Confidential CX28380 Quad T1/E1 LIU Host Serial Interface • Compatible with existing framers • Compatible with microprocessor serial ports • Bit rates Mbps In-Service Performance Monitoring • ...
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... Bipolar Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 2.3.6.2 Unipolar Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 2.4 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 2.4.1 Transmit Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 2.4.1.1 Bipolar Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 2.4.1.2 Unipolar Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 2.4.2 TZCS Encoder .21 2.4.3 Transmit Jitter Attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 2.4.4 All 1s AIS Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 2.4.5 Pulse Shaper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 2.4.6 Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 2.4.6.1 Transmit Termination Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 2.4.6.2 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 2.4.7 Transmitter Output Monitoring .27 29380-DSH-001-B Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies iv ...
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... Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 2.8.2 Device Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 3.1 Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 3.2 Global Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 3.3 Per Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 3.4 Transmitter Shape Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 4.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 4.3 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 4.4 Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 4.5 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 4.6 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 29380-DSH-001-B Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Contents v ...
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... CX28380 Logic Diagram (Host Mode 1-3 Figure 1-3. CX28380 Logic Diagram (Hardware Mode 1-4 Figure 2-1. Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 Figure 2-2 ...
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... Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-53 Table 4-2. Peak Reflow Temperature for Green (RoHS) Compliant Version of the CX28380 G device . . . . . . . . . . . . . . . . 4-54 Table 4-3. Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-54 Table 4-4 ...
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... Table A-1. Applicable Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-68 Table B-1. Transformer Specifications B-70 Table B-2. REFCKI (10 MHz) Crystal Oscillator Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-70 Table C-1. CX28380-16 Typical Register Settings for C-73 Table C-2. CX28380-16 Typical Register settings for E1-120 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-74 29380-DSH-001-B Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Tables viii ...
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... Pin Descriptions The CX28380 is packaged in a 128-pin metric quad flat pack (MQFP). A pinout diagram is illustrated in Figure 1-1. Logic diagrams are illustrated in output functions, and descriptions are provided in The following input pins contain an internal pull-up resistor (> 50 kΩ) and may remain unconnected if unused or if the active high input state is desired: ...
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... Figure 1-1. CX28380 Pinout Diagram CLADI 1 VAACL 2 GNDCL 3 REFCKI 4 VSS 5 VDD 6 CLK32 7 CLK1544 8 CLK2048 9 CLADO 10 VSS 11 VDD 12 RNEGO/BPV [4] 13 RPOSO/RDATO [4] 14 RCKO [4] 15 TNEGI [4] 16 TPOSI/TDATI [4] 17 TCLK [4] 18 RNEGO/BPV [3] 19 RPOSO/RDATO [3] 20 RCKO [3] 21 TNEGI [3] 22 TPOSI/TDATI [3] 23 TCLK [3] 24 VSS ...
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... Figure 1-2. CX28380 Logic Diagram (Host Mode) Hardware/Host Mode Hardware/Host Mode Hardware Reset I Hardware Reset Local Loopback I Local Loopback Remote Loopback I Remote Loopback Serial Data In I Serial Data In Serial Clock In I Serial Clock In Serial Chip Select I Serial Chip Select Receive Tip I Receive Tip ...
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... Figure 1-3. CX28380 Logic Diagram (Hardware Mode) VDD Hardware/Host Mode Hardware Reset I Jitter Attenuator Path I Jitter Attenuator Size I Unipolar/Bipolar I Transmitter Termination I Transmit Pulse Template I Clock Polarity I Raw Mode Select I Local Loopback I Remote Loopback I Zero Code Suppression I Receive Tip I Receive Ring I Transmit Clock ...
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... Transmitter (continued Hardware Mode, a low signal causes AIS (unframed all 1s) transmission on I XTIP/XRING outputs. In Host Mode, these pins can be enabled or disabled [LIU_CTL; addr n3]. If disabled, they are not used and may be left unconnected. ® Mindspeed Technologies Pin Descriptions Definition 5 ...
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... See the Host Serial Control Signals section of this table. JSEL( JDIR / SCLK P Low selects receiver Raw mode. Applicable only in Hardware Mode. In Raw mode, I RPOSO and RNEGO represent the data slicer outputs, and RCKO is the logical OR of RPOSO and RNEGO. ® Mindspeed Technologies Pin Descriptions Definition JSEL(2) / SDI JATERR(1) / SDO 6 ...
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... JAT (if enabled) is placed in the transmit path. See the description for JSEL(2:0). SCLK/JDIR is a dual function pin high on JATERR indicates an overflow or underflow error in the jitter attenuator elastic store. JATERR(1) / SDO is a dual function pin. ® Mindspeed Technologies Pin Descriptions Definition Table 2-3. Tables 2-4 ...
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... V ± 5%. Power supply pairs for the transmitter driver circuitry. These pin pairs should each be bypassed with a tantalum capacitor value of at least 10 I +3.3 V ± 5%. Power supply pair for the analog receiver circuitry. I +3.3 V ± 5%. Power supply pair for the CLAD PLL circuitry. ® Mindspeed Technologies Pin Descriptions Definition Table 2-1). µ F. ...
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... V. If all logic input signals are 3.3 V levels, then this pin may be connected to the 3.3 V supply. Bypass with a 10 — No-connect pins are reserved for future device compatibility and should be left unconnected. ® Mindspeed Technologies Pin Descriptions Definition µ F tantalum capacitor. 9 ...
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... Circuit Description 2.1 Overview The CX28380 includes four identical T1/E1 transceiver channels and a common CLAD packaged in a 128-pin MQFP carrier designed to interface T1/E1 framers operate as a stand-alone line interface for synchronous or plesiochronous mappers and multiplexers. The CX28380 is ideal for high line density, short-haul applications that require low power (3 ...
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... Figure 2-1. Detailed Block Diagram 29380-DSH-001-B Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Circuit Description 11 ...
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... SDI pin. This data is received by the CX28380 and stored in the addressed register. If the operation is a read operation (R/W = 1), the CX28380 outputs the addressed register contents on the SDO pin. The signal input on SDI is sampled on the SCLK rising edge, and data output on SDO changes on the SCLK falling edge ...
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... Reset The CX28380 supports three reset methods: power-on reset, hard reset initiated by the RESET pin, and soft reset initiated by the RESET bit in the Global Configuration Register [GCR; addr 01]. In Host Mode, all three reset methods produce the same results as listed below. In Hardware Mode, power-on reset and hard reset produce the same results as shown, and soft reset is not applicable ...
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... Power-on Reset An internal power-on reset process is initiated during power-up. When VDD has reached approximately 2.6 V, the internal reset process begins and continues for 300 ms maximum if REFCLK is applied. If REFCLK is not present, the CX28380 remains in the reset state. 2.2.4.2 Hard Reset Hard reset is initiated by bringing the RESET pin active (low). Once initiated, the internal reset process completes in 5 µ ...
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... This section discusses each receiver block from the line input to the digital outputs. 29380-DSH-001-B Preliminary Information / Mindspeed Proprietary and Confidential Ω line-feed resistors, a 2:1 turns ratio transformer, Ω ), and 100 protection resistors. The 100 t 100 RTIP CX28380 Rt 100 0.1 RRING ® Mindspeed Technologies Circuit Description Ω resistors are 100048_002 ...
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... RCKO is the logical NOR of the RPOSO and RNEGO. This mode is useful in applications which provide external clock and data recovery. mode receiver signals. 29380-DSH-001-B Preliminary Information / Mindspeed Proprietary and Confidential Data Slicer Level (50% of Peak ® Mindspeed Technologies Circuit Description BPV Figure 2-5 illustrates the raw 16 ...
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... Mindspeed Technologies Circuit Description BPV RALOS RLOS 100 Zeros 100 Zeros 100 Zeros 32 Zeros 32 Zeros 32 Zeros ...
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... JAT) is illustrated by the curve labeled with “Typical Receiver Tolerance with JAT Disabled.” The receiver meets jitter tolerance specifications TR62411, G.823, and G.824. In addition, the receiver 29380-DSH-001-B Preliminary Information / Mindspeed Proprietary and Confidential Sensitivity Table 2-1. RALOS status is cleared as soon as pulses above the RALOS ® Mindspeed Technologies Circuit Description RALOS RLOS 18 ...
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... HDB3). In Hardware Mode, unipolar operation is enabled by pulling the UNIPOLAR pin low. In Host Mode, unipolar operation is enabled by writing register bit UNIPOLAR [RLIU_CR; addr n1]. 29380-DSH-001-B Preliminary Information / Mindspeed Proprietary and Confidential Section 2.6. Chapter 1 for details. Table 1-1. ® Mindspeed Technologies Circuit Description 19 ...
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... A high on TDATI causes an AMI pulse to be transmitted to the line. In this mode, the TZCS encoder can be enabled to provide B8ZS or HDB3 zero code suppression. In Hardware Mode, unipolar operation is 29380-DSH-001-B Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Circuit Description Figure 2-6 20 ...
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... TAIS_PE to 1 disables the TAIS register bit and allows manual transmission of AIS using the TAIS [n] hardware pins. See LIU_CTL [addr n3] in 29380-DSH-001-B Preliminary Information / Mindspeed Proprietary and Confidential Table 1-1. Chapter 3, and Table 1-1. ® Mindspeed Technologies Circuit Description Chapter 1; for JAT transfer Section 2.5. 21 ...
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... Hardware Mode Line Length Configuration 0–133 ft. 133–266 ft. 266–399 ft. 399–533 ft. 533–655 ft. ® Mindspeed Technologies Circuit Description Transmitter Mode Transmit Transmit Data Clock X Tx Data TCLK 0 AIS TCLK X No Data TCLK 1 AIS TACKI/EACKI X Tx Data ...
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... XTIP[n] and XRING[n]. When a shorted line is detected, transmit monitor and protection circuits reduce the output current level to less than 50 mA RMS. The standard transmit transformer for the CX28380 has a turns ratio of 1:2 (chip-side:line-side). To minimize power consumption, an alternate 1:1.36 turns ratio transformer can be used in an unterminated configuration. ...
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... Resistors (Rs) in series with Tx TIP and Tx RING line connections are sometimes used with surge protection circuits. Without compensation, the addition of these resistors decreases the transmit pulse amplitude. The CX28380 provides an option in Host Mode to boost the output level if resistors are installed. Compensation is optimized for the use of 5.6 Ω Rs values. In Hardware Mode, these resistors are required. ...
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... None None None 31.6 None 51.1 None None Parallel Termination Ω (Rt, None 23.7 None 23.7 None 23.7 None 23.7 Parallel Termination Ω (Rt, Ω None 2 × 5.6 Ω 28.7 2 × 5.6 ® Mindspeed Technologies Circuit Description Return Loss (dB –10 –10 0 Return Loss (dB) ) –30 –18 –18 –30 Return Loss (dB –10 25 ...
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... Parallel Termination Ω (Rt, Ω × 5.6 Ω × 5.6 Ω × 5.6 Ω × 5.6 Parallel Termination Ω (Rt, None 68.1 None 107.0 None None ® Mindspeed Technologies Circuit Description Return Loss (dB) ) –10 0 Return Loss (dB) ) –30 –18 –18 –30 Return Loss (dB) ) –10 – ...
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... Table 2-9. Refer also to register LIU_CTL [addr n3] in Table 2-9. Loopback Control Pins LLOOP RLOOP 29380-DSH-001-B Preliminary Information / Mindspeed Proprietary and Confidential Chapter 3. None Remote Line Loop Local Analog Loop Local Digital Loop ® Mindspeed Technologies Circuit Description Loopback 27 ...
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... The dejittered receiver recovered clock is output on the RCKO[n] pin if the JAT is configured in the receive path. The receiver input clock and data jitter tolerance and jitter transfer meet TR 62411-1990. illustrate jitter tolerance and JAT transfer characteristics. 29380-DSH-001-B Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Circuit Description ± 64 bits of accumulated Figures 2-9 and ...
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... Minimum Tolerance 1 0.1 0.1 8380_013 29380-DSH-001-B Preliminary Information / Mindspeed Proprietary and Confidential Typical Receiver Tolerance with JAT Disabled 128 bits 64 bits 1 100 Sine Wave Jitter Frequency (Hz) [Log Scale] ® Mindspeed Technologies Circuit Description 32 bits 16 bits 8 bits 0.4 UI 0.2 UI 0.1 UI 1000 10000 100000 29 ...
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... Atten. Boundary) -60 1 29380-DSH-001-B Preliminary Information / Mindspeed Proprietary and Confidential JAT Size = 128 10 100 1000 Sine Wave Jitter Frequency (Hz) [Log Scale] ® Mindspeed Technologies Circuit Description Rec G.735 (Min. Atten Boundary) PUB 62411 (Min. Atten. Boundary 10000 100000 ...
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... Preliminary Information / Mindspeed Proprietary and Confidential Clock Rate Adapter (CLAD) [G_T1/E1] CLAD Control/ [CPD_IE] Loop NCO Phase Filter Detector [FREE] [LFGAIN] Divider Chain 13 ® Mindspeed Technologies Circuit Description [CPDERR] Status [CPD_INT] 10 MHz REFCKI 32.768 MHz CLK32 2.048 MHz CLK2048 1.544 MHz CLK1544 CLADO 14 ...
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... Mindspeed Technologies Circuit Description Table 2-10 lists the CLADV VSEL (kHz) 1024 0001 1024 0001 1024 0001 1024 0001 1024 0001 1024 0001 1024 ...
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... Table 2-11. Table 2-11. ® Mindspeed Technologies Circuit Description CLADV VSEL (kHz) 1544 0111 1544 0111 1544 0111 1544 0111 1544 0111 3088 1000 6176 1001 12,352 1010 24,704 ...
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... High values allow the CLAD to react more quickly (by raising the 3 dB point of its jitter transfer curve) while low values cause the CLAD to react more slowly. 29380-DSH-001-B Preliminary Information / Mindspeed Proprietary and Confidential Table 2-11 Phase Compare Frequency VSCALE (kHz) 1024 011 ® Mindspeed Technologies Circuit Description are applicable. For instance, an Table 2-12. CLADV VSEL (kHz) 8192 0100 34 ...
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... Figure 2-1. Jitter Transfer 3 dB Point Versus LFGAIN and RSCALE/VSCALE for T1 -10.00 -30.00 -50.00 -70.00 -90.00 -110.00 -130.00 1 -10.00 -30.00 -50.00 -70.00 -90.00 -110.00 -130.00 1 29380-DSH-001-B Preliminary Information / Mindspeed Proprietary and Confidential T1_3dB, RSCALE=1,VSCALE=1 1000 Frequency (Hz) T1_3dB, LFGAIN=1 1000 Frequency(Hz) ® Mindspeed Technologies Circuit Description LFGAIN=1 LFGAIN=8 LFGAIN=512 RVSCALE=1 RVSCALE=4 RVSCALE=128 35 ...
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... RVSCALE means RSCALE and VSCALE. For example, RVSCALE = 128 means that RSCALE = 128 and VSCALE = 128. 2.8 Test Access Port (JTAG) The CX28380 incorporates printed circuit board testability circuits in compliance with IEEE Std. P1149.1a–1993, IEEE Standard Test Access Port and Boundary–Scan Architecture, commonly known as JTAG (Joint Test Action Group). ...
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... Preliminary Information / Mindspeed Proprietary and Confidential Table 2-13 lists the JTAG instructions and their codes. Table 2-14. Part Number 0x8380 16 Bits ® Mindspeed Technologies Circuit Description Code 1111 0001 0000 0010 Manufacturer 0x013 ...
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... Line Interface Unit Control — — R Alarm Status R Interrupt Status Register R/W Interrupt Enable Register R/W Transmit Pulse Shape Configuration R/W Transmit Pulse Shape Configuration R/W Transmit Pulse Shape Configuration R/W Transmit Pulse Shape Configuration ® Mindspeed Technologies (1) Default Setting (Hex — — — ...
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... Global Control and Status Registers 00—Device Identification (DID DID[7] DID[6] DID[5] Device value of 0x0 is assigned. DID[7:4] Device Revision- A value of 0x6 is assigned for CX28380-16 DID[3:0] 01—Global Configuration (GCR RESET G_T1/E1N CLK_OE 29380-DSH-001-B Preliminary Information / Mindspeed Proprietary and Confidential R/W ...
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... Determines output state of CLK1544, CLK2048, and CLADO clock — Enables CLAD loss of lock detector, CPD_INT — Determines whether TCLK[1:4] pins are inputs or outputs. — Selects the CLAD reference clock source input to the CLAD phase — RSCALE[0] LFGAIN[3] ® Mindspeed Technologies Registers LFGAIN[2] LFGAIN[1] LFGAIN[0] R/W 40 ...
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... Preliminary Information / Mindspeed Proprietary and Confidential Scale Factor CLADR Reference 1 CLADR = CLADI 2 CLADR = CLADI/2 4 CLADR = CLADI/4 8 CLADR = CLADI/8 16 CLADR = CLADI/16 32 CLADR = CLADI/32 64 CLADR = CLADI/64 128 CLADR = CLADI/128 ® Mindspeed Technologies Registers [RSCALE] to form CLADR 41 ...
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... E1 8192 16,384 32,768 1544 3088 6176 12,352 24,704 2560 1536 (unframed) <Invalid> <Invalid> Picks one of 14 CLAD divider chain frequencies to output — ® Mindspeed Technologies Registers R OSEL[2] OSEL[1] OSEL[0] 42 ...
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... CLADV / 2 4 CLADV / 4 8 CLADV / 8 16 CLADV / 16 32 CLADV / 32 64 CLADV / 64 128 CLADV / 128 CTEST[4] CTEST[ — CPDERR — ® Mindspeed Technologies Registers R VSCALE[2] VSCALE[1] VSCALE[0] [VSCALE] before use in the R CTEST[2] CTEST[1] CTEST[ — — CPD_INT R 0 ...
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... Preliminary Information / Mindspeed Proprietary and Confidential Real-time indicator of the CLAD phase detector status. CPDERR — F_ADDR[4] F_ADDR[ A_TEST[4] A_TEST[ A_TEST[12] A_TEST[11 F_TR[4] F_TR[3] ® Mindspeed Technologies Registers F_ADDR[2] F_ADDR[1] F_ADDR[ A_TEST[2] A_TEST[1] A_TEST[ A_TEST[10] A_TEST[9] A_TEST[ F_TR[2] ...
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... Preliminary Information / Mindspeed Proprietary and Confidential F_TR[10] F_TR[ F_TR[15] F_TR[14 F_TR[20] F_TR[19 F_TR[25] F_TR[24 D_CH[1] D_CH[0] ® Mindspeed Technologies Registers F_TR[8] F_TR[7] F_TR[ F_TR[13] F_TR[12] F_TR[11 F_TR[18] F_TR[17] F_TR[16 F_TR[23] F_TR[22] F_TR[21] 2 ...
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... JEN enables the JAT in the receive or the transmit path (determined — Writing JCENTER resets the elastic store write pointer and forces — ± (128 bits) of accumulated phase offset. Elastic Store Size 8 Bits 16 Bits 32 Bits 64 Bits 128 Bits ® Mindspeed Technologies Registers JSIZE[2] JSIZE[1] JSIZE[0] R/W 46 ...
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... Enables HDB3 or B8ZS zero code suppression encoding/ — RPOSO/RNEGO data outputs are replaced by the data slicer output, and — Disables the receiver equalizer. (Test mode only) Compensates for 20 dB resistive signal attenuation caused by placement — ® Mindspeed Technologies Registers R ATTN — ...
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... Unused channels can be put into a low power mode in order to minimize Adjusts the transmit output level to compensate for series — Enables custom transmit pulse transmission. The — Each positive or negative pulse output on XTIP/ — ® Mindspeed Technologies Registers R PULSE[2] PULSE[1] PULSE[0] ...
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... Twisted Pair 100 Ω Twisted Pair LLOOP RLOOP If AISCLK is active, the transmitter clock is automatically — When activated manually (TAIS) or automatically — lists transmitter operating modes resulting from various configuration ® Mindspeed Technologies Registers Application T1 DSX T1 DSX T1 DSX T1 DSX T1 DSX CSU/NCTE 2 1 ...
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... BPV is asserted only for bipolar violations which are not part of the ZCS code. 29380-DSH-001-B Preliminary Information / Mindspeed Proprietary and Confidential RLOOP Loopback 0 No loopback 1 Remote Line Loopback 0 Local Analog Loopback 1 Local Digital Loopback TLOS TSHORT ® Mindspeed Technologies Registers JERR BPV — ...
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... TLOS Enables Transmit Short Circuit TSHORT Enables Jitter Attenuator Error JERR Enables Bipolar Violation BPV 29380-DSH-001-B Preliminary Information / Mindspeed Proprietary and Confidential TLOS TSHORT TLOS TSHORT ® Mindspeed Technologies Registers JERR BPV — R JERR BPV — ...
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... SH4 SH3 SH4 SH3 SH4 SH3 SH4 SH3 A_TEST[20] A_TEST[19 A_TEST[28] A_TEST[17] ® Mindspeed Technologies Registers SH2 SH1 SH0 SH2 SH1 SH0 SH2 SH1 SH0 SH2 SH1 SH0 A_TEST[18] A_TEST[17] ...
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... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 29380-DSH-001-B Preliminary Information / Mindspeed Proprietary and Confidential Specifications Parameter pins or V pins ® Mindspeed Technologies Minimum Maximum Units –0.5 5.0 V — 0.5 V –1 ...
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... Table 4-2. Peak Reflow Temperature for Green (RoHS) Compliant Version of the CX28380 G device Device Package Type CX28380 128-Pin MQFP 1. For more detailed information, please refer to Mindspeed SMT Application Note for the Pb-free devices and the detail explanation of how JEDEC determines the reflow temperatures based on Package thickness: http://mindspeed ...
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... Electrical/Mechanical Specifications Transmitter Termination Option A B 0.95 1.20 0.70 0.75 1.05 1.15 Parameter Min –40 –40 — — Minimum — — — µ A) 2.5 µ A) — 2.0 2.2 –0.5 –100 @ 0 V ® Mindspeed Technologies Units 1.00 1.20 0.70 W 0.70 0.75 0.60 W 1.10 1.20 0.85 W Max Units +120 °C +125 °C 36 °C/W 3 °C/W Typical Maximum Units 45 60 ...
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... Preliminary Information / Mindspeed Proprietary and Confidential Electrical/Mechanical Specifications Minimum –10 –10 — — — 37 — — Minimum Receiver 0 0 C-1). –18 23 –0.1 –0.4 — — — — — Transmitter ® Mindspeed Technologies Typical Maximum Units 1 10 µ µ 160 mA 0 µ ...
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... GENERAL NOTE: 1. See Figure 4-1. 29380-DSH-001-B Preliminary Information / Mindspeed Proprietary and Confidential Minimum 10 — — 2.7 coax(1) 2.14 –0.237 Ω UTP(1) 2.7 –0.3 –5 — 12 –25 — Parameter ® Mindspeed Technologies Electrical/Mechanical Specifications Typical Maximum Units 100 — — k — 3.0 3.3 2.37 2.6 0 +0.237 3.0 3.3 0 +0.3 — ...
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... GENERAL NOTE: 1. Output signals: RCKO[n], RPOSO[n], RNEGO[n], XTIP[n], XRING[n], CLK1544, CLK2048, CLADO, JATERR[2:4], SDO, 2. Sees Figure 4-3 and 4-4. 29380-DSH-001-B Preliminary Information / Mindspeed Proprietary and Confidential Electrical/Mechanical Specifications 1 Parameter 1 Parameter ® Mindspeed Technologies 2 Minimum Maximum Units 488 — ns Minimum Maximum Units 500 — ...
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... RLOS Timing Parameters Symbol 1 RLOS width low (T1 mode) RLOS width low (E1 mode) GENERAL NOTE: 1. See Figure 4-5 29380-DSH-001-B Preliminary Information / Mindspeed Proprietary and Confidential Electrical/Mechanical Specifications 1 2 Three-State 2 Note 1 Note 1 Parameter ® Mindspeed Technologies 3 Minimum Maximum Units 640 — ns 480 — ...
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... CLK1544, CLK2048, CLADO, CLK32 GENERAL NOTE: 1. See Figure 4-6. Figure 4-6. CLAD Timing Diagram 90% 10% 3 8380_018 29380-DSH-001-B Preliminary Information / Mindspeed Proprietary and Confidential Electrical/Mechanical Specifications 1 Parameter ® Mindspeed Technologies Minimum Maximum Units 9.999 10.001 MHz 8 16,384 kHz — 16,384 MHz 32.768 ...
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... TCLK[n] duty cycle (output) 29380-DSH-001-B Preliminary Information / Mindspeed Proprietary and Confidential Electrical/Mechanical Specifications Parameter Minimum 1.544 MHz – 309 Hz 2.048 MHz – 409 ® Mindspeed Technologies Minimum Maximum Units 1,544 or 2,048 kHz (Locked to line rate — — ...
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... Preliminary Information / Mindspeed Proprietary and Confidential Electrical/Mechanical Specifications Minimum — Minimum 10 — 125 100 — SCLK Cycles ® Mindspeed Technologies Maximum Units 20 ns — ns — ns Maximum Units — MHz — ns — ns — ns — ns — ...
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... Preliminary Information / Mindspeed Proprietary and Confidential Electrical/Mechanical Specifications Minimum — — Read Timing Address/Control Byte Register Data Byte Write Timing Address/Control Byte Register Data Byte ® Mindspeed Technologies Maximum Units ...
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... Figure 4-11. Host Serial Port Read Timing SCLK 4 SDI SDO 29380-DSH-001-B Preliminary Information / Mindspeed Proprietary and Confidential Address/Command Write Data Byte Byte Address/Command Byte 8 D5 ® Mindspeed Technologies Electrical/Mechanical Specifications Read Data Byte 100048_003 64 ...
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... TDO enable (Low Z) after TCK falling edge 7 TDO disable (High Z) after TCK low GENERAL NOTE: 1. See Figure 4-13. 29380-DSH-001-B Preliminary Information / Mindspeed Proprietary and Confidential 1 Address/Command Byte Parameter ® Mindspeed Technologies Electrical/Mechanical Specifications Read Data Byte 100048_004 Minimum Maximum Units 80 — 80 — 5 — ...
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... Figure 4-13. JTAG Interface Timing Diagram TDO 6 TCK TDI TMS 8380_024 29380-DSH-001-B Preliminary Information / Mindspeed Proprietary and Confidential Electrical/Mechanical Specifications ® Mindspeed Technologies 7 66 ...
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... DETAIL Ref. 128-PIN MQFP (GP00-D448) ® Mindspeed Technologies ALL DIMENSIONS IN MILLIMETERS MIN. NOM. MAX 3.40 3.04 0.25 0.33 2.57 2.87 2.71 23.20 REF. 20.0 REF. 18.5 REF 17.20 RE. 14.0 REF 12.5 REF 0.73 1.03 0.88 1.6 REF 0.50 BSC 0.13 0.28 ---- 0.13 ---- 0.23 ...
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... DS1 Automatic Facility Protection Switching (AFPS) Rqts. and Objectives Transport Systems Generic Requirements ISDN Primary Rate Interface Guidelines for Customer Premises Equipment ETSI ISDN Primary Rate User-Network Interface Specification and Test Principles Access Digital Section for ISDN Primary Rate ITU-T ® Mindspeed Technologies Title 68 ...
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... Unbalance about Earth of Telecommunication Installations Resistibility of Switching Equipment to Overvoltages and Overcurrents Application of Maintenance Principles to ISDN Primary Rate Access IEEE Standard Test Access Port and Boundary Scan Architecture (JTAG) Environment Simulation Metallic Voltage Surge Signal Power Limitations ® Mindspeed Technologies Applicable Standards Title Synchronous Digital 69 ...
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... REFCKI crystal oscillator specifications. RX Value (line) 2:1 CT (circuit) Pulse (1) T1124 1 Ω maximum OCL 1 °C 1500 V rms 0.8 µH 10 MHz ±50 ppm ±32 ppm 3.3 V Logic, CMOS or TTL 2 ppm/year, 10 ppm maximum GG ® Mindspeed Technologies TX Value (circuit) 1:2 (line) Value pin description in Chapter 1. 70 ...
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... A Appendix C: Application 29380-DSH-001-B Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies 71 ...
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... Figure C-1. Minimum Hardware Configuration 29380-DSH-001-B Preliminary Information / Mindspeed Proprietary and Confidential ® Mindspeed Technologies Application 8380_026 72 ...
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... Table C-1. CX28380-16 Typical Register Settings for T1 Register Offset Name 1 GCR 2 CLAD_CR 3 CSEL 4 CPHASE 5 CTEST 6 CSTAT 7 FREG 8 TESTA1 9 TESTA2 A FUSE-CH1 B FUSE-CH2 C FUSE-CH3 D FUSE-CH4 E FUSE-RES F TESTD 10,20,30,40 JAT_CR 11,21,31,41 RLIU_CR 12,22,32,42 TLIU_CR 13,23,33,43 LIU_CTL 15,25,35,45 ALARM 16,26,36,46 ISR 17,27,37,47 IER 18,28,38,48 SHAPE[0] 19,29,39,49 SHAPE[1] 1A,2A,3A,4A SHAPE[2] 1B,2B,3B,4B SHAPE[3] 1C,2C,3C,4C SHAPE[4] 1D,2D,3D,4D SHAPE[5] 1E,2E,3E,4E SHAPE[6] 1F,2F,3F,4F SHAPE[7] 29380-DSH-001-B Preliminary Information / Mindspeed Proprietary and Confidential ...
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... Table C-1. CX28380-16 Typical Register Settings for T1 Register Offset Name 50 TESTA3 51 TESTA4 52-7F RESERVED Table C-2. CX28380-16 Typical Register settings for E1-120 Register Offset Name 1 GCR 2 CLAD_CR 3 CSEL 4 CPHASE 5 CTEST 6 CSTAT 7 FREG 8 TESTA1 9 TESTA2 A FUSE-CH1 B FUSE-CH2 C FUSE-CH3 D FUSE-CH4 E FUSE-RES F TESTD 10,20,30,40 JAT_CR 11,21,31,41 RLIU_CR 12,22,32,42 TLIU_CR 13,23,33,43 LIU_CTL ...
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... Table C-2. CX28380-16 Typical Register settings for E1-120 Register Offset Name 19,29,39,49 SHAPE[1] 1A,2A,3A,4A SHAPE[2] 1B,2B,3B,4B SHAPE[3] 1C,2C,3C,4C SHAPE[4] 1D,2D,3D,4D SHAPE[5] 1E,2E,3E,4E SHAPE[6] 1F,2F,3F,4F SHAPE[7] 29380-DSH-001-B Preliminary Information / Mindspeed Proprietary and Confidential Basic E1 Configuration Value ® Mindspeed Technologies Application Description 75 ...
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... HDSL high bit-rate digital subscriber line inter-integrated circuit ISDN Integrated Services Digital Network ITU–T International Telegraph and Telephone Consultative Committee JAT jitter attenuator JTAG Joint Test Action Group 29380-DSH-001-B Preliminary Information / Mindspeed Proprietary and Confidential Definition ® Mindspeed Technologies 76 ...
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... Synchronous Optical Network TAP test access port TLOC transmit loss of clock TLOS transmit loss of signal TZCS transmit zero code suppression UI unit interval UTP unshielded twisted pair ZCS zero code suppression 29380-DSH-001-B Preliminary Information / Mindspeed Proprietary and Confidential Definition ® Mindspeed Technologies Acronym List 77 ...
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... Newport Beach, CA 92660 © 2006 Mindspeed Technologies ® , Inc. All rights reserved. Information in this document is provided in connection with Mindspeed Technologies ® ("Mindspeed ® ") products. These materials are provided by Mindspeed as a service to its customers and may be used for informational purposes only. Except as provided in Mindspeed’s Terms and Conditions of Sale for such products or in any separate agreement related to this document, Mindspeed assumes no liability whatsoever ...