cx28500 Mindspeed Technologies, cx28500 Datasheet

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... CX28500 Multichannel Synchronous Communications Controller Data Sheet 28500-DSH-002-C ® Mindspeed Technologies Mindspeed Proprietary and Confidential October 2006 ...

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... Ordering Information Model Number CX28500EBG CX28500G-12* *The G in the part number indicates that this is an RoHS compliant package. Refer to www.mindspeed.com for additional information. Revision History Revision 500052A 500052B 500052C 28500-DSH-002-A 28500-DSH-002-B 28500-DSH-002-C 28500-DSH-002-C Package 35 mm TBGA 35 mm TBGA (RoHS compliant) Level Date — ...

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... DS0 time slot (8 bits). For example Kbps channel can be achieved by mapping 7 bits out of 8 possible bits in a time slot ( Kbps = 56 Kbps). CX28500 also includes a 32-bit expansion port for bridging the PCI bus to local microprocessors or peripherals ...

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... Line Card SONET/ATM SAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 1.7 Feature Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 1.8 System Overview .16 1.9 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.10 Receive Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.11 Transmit Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.12 Pin Configuration .21 1.13 CX28500 Hardware Signals Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 2.0 Internal Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2.1 Serial Interface Unit (SIU .37 2.2 Serial Line Processor (SLP .38 2.3 Direct Memory Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 2.3.1 General Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 2.4 Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 3 ...

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... Channel Clear To Send (CTS .63 5.1.6 Frame Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 5.1.7 Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 5.2 Serial Port Interface Definition in TSBUS Mode .66 5.2.1 TSBUS Frame Synchronization Flywheel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 5.2.2 TSBUS Change Of Frame Alignment (COFA .66 5.2.3 TSBUS Out Of Frame (OOF)/Frame Recovery (FREC .67 5.2.4 TSBUS Frame Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 28500-DSH-002-C ® Mindspeed Technologies Mindspeed Proprietary and Confidential Table of Contents v ...

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... TDMA Buffer Allocation Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 6.7.4 TDMA Configuration Register .102 6.7.5 TSIU Time Slot Configuration Register .103 6.7.5.1 Time Slot Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 6.7.5.2 TSIU Time Slot Configuration Descriptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 6.7.6 TSIU Time Slot Pointer Assignment Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 28500-DSH-002-C ® Mindspeed Technologies Mindspeed Proprietary and Confidential Table of Contents vi ...

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... Channel Jump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 7.2.3.1 Receive Channel Jump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 7.2.3.2 Transmit Channel Jump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 7.2.4 Channel Reactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 7.2.5 Unmapped Time Slots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 8.0 Basic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 8.1 Protocol-Independent Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 8.1.1 Transmit .129 8.1.2 Receive .129 8.2 HDLC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .129 28500-DSH-002-C ® Mindspeed Technologies Mindspeed Proprietary and Confidential Table of Contents vii ...

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... Ending a Message with an Abort or Sending an Abort Sequence . . . . . . . . . . . . . . . . . . . . .141 8.3.2 Transmit Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141 8.3.2.1 End Of Buffer [EOB .142 8.3.2.2 End Of Message [EOM .142 8.3.3 Receive Events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142 8.3.3.1 End Of Buffer [EOB .142 8.3.3.2 End Of Message (EOM .142 8.3.3.3 Frame Recovery (FREC .143 28500-DSH-002-C ® Mindspeed Technologies Mindspeed Proprietary and Confidential Table of Contents viii ...

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... EBUS Arbitration Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 10.2.5 Serial Interface Timing and Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159 10.2.6 Test and Diagnostic Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164 10.3 Package Thermal Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165 10.4 Mechanical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166 Appendix A: CX28500 PCI Bus Latency and Utilization Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 A.1 Objective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167 A.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .167 A.3 Assumptions/Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168 A ...

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... Appendix B: Example of an Arbitration for Fast Back-to-Back and Non-Fast Back-to-Back Transactions. 182 Appendix C: T3 Frame Relay Switch Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 Appendix D: Example of Little-Big Endian Byte Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Appendix E: TSBUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 E.1 Connection Between CX28500 and Other TSBUS Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .192 E.1.1 VSP Mapping of Intermixed Digital Level 2 Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196 E.2 Timing Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .197 E ...

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... System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 Figure 1-8. CX28500 Top Level Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 Figure 1-9. Pin Configuration Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21 Figure 2-1 ...

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... Figure C-3. T3/E3 Framer Connection with HDLC Controller (T3/E3 Payload Path C-189 Figure C-4. T3/E3 Framer Connection with HDLC Controller (T3/E3 Overhead Path C-190 Figure E-1. CX28500 Time Slot Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-193 Figure E-2. Source/Destination of TSBUS Block Line-Side Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-195 Figure E-3. Payload Time Slot Bus Transmit Data (TSB_TDAT E-198 Figure E-4 ...

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... I/O Pin Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28 Table 1-8. CX28500 Hardware Signal Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-29 Table 3-1. PCI Configuration Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-44 Table 3-2 ...

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... Table 10-4. PCI Interface DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-151 Table 10-5. PCI Clock (PCLK) Waveform Parameters, 3.3 V Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-152 Table 10-6. PCI Reset Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-153 Table 10-7. PCI Input/Output Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-153 Table 10-8. PCI I/O Measure Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-153 Table 10-9. EBUS Reset Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-155 28500-DSH-002-C ® Mindspeed Technologies Mindspeed Proprietary and Confidential List of Tables xiv ...

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... Table 10-13. Serial Interface Input/Output Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-159 Table 10-14. Serial Interface Input/Output Measure Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-160 Table 10-15. Test and Diagnostic Interface Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-164 Table 10-16. Test and Diagnostic Interface Switching Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-164 Table 10-17. CX28500 Package Thermal Resistance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-165 Table A-1. Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-173 Table A-2. ...

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... Peripheral Component Interface (PCI) bus to system memory at a rate MHz. Each serial port can be configured to support different types of interfaces. All of the CX28500’s serial ports are individually programmable to operate as conventional or TSBUS serial ports. 28500-DSH-002-C ® ...

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... The bit-stream belongs to a single logical channel. The CX28500 conventional, unchannelized mode can operate Mbps for all 32 serial ports. The first six ports can operate unchannelized T3/E3, HSSI, or STS-1/STM-1 bit-stream ...

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... CX28500 Serial Port Throughput Limits Each of the CX28500 serial ports can be configured to operate in any of the preceding operational modes. The following restrictions apply: 1. The overall number of time slots cannot exceed 4096. 2. The overall number of channels cannot exceed 1024. 3. Only the first 6 ports can be configured to operate as high speed ports—T3 (44.7 Mbps), E3 (34.4 Mbps), and HSSI (52 Mbps) ...

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... CX28500’s configuration options are extremely flexible. Each logical channel can be assigned to a physical stream ranging from 8 Kbps (sub-channeling mode Mbps. CX28500’s serial ports can interface to a standard PCM highway or TSBUS bus, which can be configured to operate at any of the serial port rates given in Table 1-4 ...

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... Half of the OC-12 data rate, including overhead. The send and receive data can be formatted in the HDLC messages or left unformatted (transparent mode) over any combination of bits within a selected time slot. CX28500’s protocol message type is specified on a per-channel basis. 1.3 CX28500’s Bus Interfaces 1.3.1 PCI— ...

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... For the receive direction CX28500 requires the stuff status for each time slot to be presented at its RSTUFF input on the current time slot for which the stuff is applied (For a detailed description, see the timing diagrams in 1 ...

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... CX28500’s Applications The potential applications for CX28500 are in data communications and telecommunications markets, such as the following: • WAN access equipment • Router • Remote Access Server • Frame Relay Switch • ISDN basic-rate (BRI) or primary-rate interfaces (PRI) • Edge Switch (ATM or Frame Relay) • ...

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... The TSBUS also provides paths for inter-processor control (IPC) channels between the DS3 framers and the central Host processor. This example illustrates how 30 of CX28500’s 32 serial ports are used in a Mid-Range Router Application. The T3/E3 data path (payload) occupies only one TSBUS port and the overhead path occupies another TSBUS port. • ...

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... RAM to perform HDLC packet formatting and de-formatting. 1.6.2 T3/E3 Frame Relay Switch This application illustrates a connection between CX28500 and CX28344 T3/E3 Framer specifying an 6 DS3 serial ports application for an unchannelized DS3 High-End Router. Feature List: • ...

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... T3/E3 Framer T3/E3 CX28333 T3/E3 T3/E3 LIU LEGEND: CX28333 – DS3/E3 Line Interface Unit CX28332 – DS3/E3 Line Interface Unit CX28343 – T3 Framer CX28500 – HDLC Controller 28500-DSH-002-C CX28343 T3 Framer CX28343 T3 Framer 6 Ports T3/E3 Overhead (TDL) See figure C-4, T3/E3 Framer Connection with HDLC Controller (T3/E3 Overhead Path) ...

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... CX28333 (T3/E3 Line Interface Framer) and eight units of eight DSL modems. The modems are connected to CX28500’s serial port at the 16 Mbps rate into a PCM highway. CX28500’s first three ports run channelized T3 and the other 16 ports run at 16 Mbps so that the total port aggregated rate is 260.6 Mbps. The example shows how a bank of eight modems can be configured by the serial line Control Serial Port (CSP) ...

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... EBUS bus configuration to local devices • PCI bus which acts as CX28500’s configuration/status interface • Power solutions for HDLC processing messages (two HDLC controllers running at 66 MHz) • IPC channel processor • Performance monitoring • Scalable configuration up to OC-48 • T3/E3 data link over the TSBUS channel ...

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... Increased PCI utilization accomplished by supporting different classes of traffic with fully per-channel programmable threshold values of internal buffers. These configurable buffer thresholds allow the user to take advantage of PCI bursts in transferring data between CX28500’s internal memory and shared memory. Figure 1-6. Line Card SONET/ATM SAR ...

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... A 1024-channel, full-duplex link layer controller for synchronous applications is provided. • 32 full-duplex physical interfaces (i.e., ports) with independent clock rates are provided. CX28500 implements 32 serial ports that are individually programmable to operate either as conventional serial ports or TSBUS serial ports. Conventional serial ports’ input/out data streams can be configured as channelized or unchannelized bit streams ...

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... KB per direction receive and transmit (64 Kb per chip) internal FIFO • Configurable DMA threshold per-channel basis • Programmable FIFO size per-channel basis • Configurable number of buffer descriptors per channel • Flexible buffer descriptor handling • Self Service mechanism 28500-DSH-002-C ® Mindspeed Technologies Mindspeed Proprietary and Confidential Introduction 15 ...

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... Low power CMOS technology is used 1.8 System Overview CX28500 supports 32 fully independent serial ports that can be configured to run in channelized, unchannelized TSBUS mode. For example, in the channelized mode, the first six ports can operate at 51.84 Mbps (STS-1 rate) while another 22 ports can operate at 8.192 Mbps (4xE1 rate). Four more ports will be unused. Each STS-1 frame transports 28xT1, 1xT3, 21xE1 or mixed T1/E1 VTG paths ...

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... DS1s and E1s extracted from mixed VTGs via the SONET framers 28500-DSH-002-C JTAG HDLC Serial RxDMA Line TxDMA Processors Host Interface (TSLP RSLP) Expansion Bus Interface (EBUS) CX28500 EBUS ® Mindspeed Technologies Mindspeed Proprietary and Confidential Introduction Serial Physical Interface 0 Interface 0 Serial Interface Unit (SIU) Physical Interface 30 Physical ...

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... The following is a description of the block diagram. • Host Interface (PCI): This block provides the communication path between the Host and CX28500. • Expansion Bus (EBUS): The EBUS is an extension of the Host Interface, which provides the Host with access to control other devices on the local PC board. ...

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... SIU controls the data access to the Rx and Tx Serial Line Processors. Given that CX28500 supports two types of serial ports, one is the conventional interface, the other TSBUS interface—SIU needs to operate depending on serial port type (for detailed descriptor information, see • ...

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... TxSIU for transmission. The SIU uses a fixed priority scheme where port A has priority over port B (when A is smaller than B). For the selected port, the SIU uses a internal map conversion to identify which channel number data is transferred. 28500-DSH-002-C ® Mindspeed Technologies Mindspeed Proprietary and Confidential Introduction 20 ...

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... Pin Configuration Figure 1-9 provides a diagram of the CX28500 Pin Configuration, and Figure 1-9. Pin Configuration Diagram ...

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... B23 ROOF/CTS/STB/SPORT [7] B24 RCLK[7] B25 GND B26 RCLK[6] B27 TDAT[5] B28 GND B29 RDAT[5] B30 TSYNC/TSTUFF[4] B31 GND B32 GND ® Mindspeed Technologies Mindspeed Proprietary and Confidential Introduction Pin Pin Number Label B33 GND B34 GND C1 GND C2 GND C3 GND C4 TSYNC/TSTUFF[17] C5 ROOF/CTS/STB/SPORT ...

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... E26 VDD_io E27 GND E28 VDD_c E29 GND E30 GND E31 No Connect E32 TSYNC/TSTUFF[3] E33 TCLK[3] E34 RCLK[3] F1 TDAT[18] ® Mindspeed Technologies Mindspeed Proprietary and Confidential Introduction Pin Pin Number Label F2 TSYNC/TSTUFF[18] F3 TCLK[18] F4 RCLK[18] F5 GND F30 VDD_io F31 No Connect F32 RSYNC/RSTUFF[3] ...

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... VDD_c R30 GND R31 TCLK[24] R32 RCLK[24] R33 RSYNC/RSTUFF[24] R34 RDAT[24] T1 ROOF/CTS/STB/SPORT [23] T2 GND T3 TDAT[23] T4 TSYNC/TSTUFF[23] T5 GND ® Mindspeed Technologies Mindspeed Proprietary and Confidential Introduction Pin Pin Number Label T30 VDD_c T31 ROOF/CTS/STB/SPORT [25] T32 TDAT[25] T33 GND T34 TSYNC/TSTUFF[25] U1 TDO U2 TMS U3 ...

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... EAD[16] AF3 EAD[15] AF4 EAD[14] AF5 GND AF30 VDD_io AF31 RCLK[30] AF32 TCLK[30] AF33 TSYNC/TSTUFF[30] AF34 TDAT[30] ® Mindspeed Technologies Mindspeed Proprietary and Confidential Introduction Pin Pin Number Label AG1 EAD[13] AG2 EAD[12] AG3 EAD[11] AG4 EAD[10] AG5 VDD_c AG30 GND ...

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... AL34 RBS[0] AM1 GND AM2 GND AM3 GND AM4 GND AM5 GND AM6 PCLK AM7 AD[30] AM8 AD[27] AM9 C/BE[3]* AM10 AD[21] ® Mindspeed Technologies Mindspeed Proprietary and Confidential Introduction Pin Pin Number Label AM11 AD[18] AM12 FRAME* AM13 STOP* AM14 PAR AM15 AD[13] AM16 AD[09] AM17 AD[07] AM18 AD[02] ...

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... PERR* AP14 AD[15] 28500-DSH-002-C Pin Pin Number Label AP15 AD[11] AP16 AD[08] AP17 AD[05] AP18 AD[04] AP19 AD[00] AP20 C/BE[7]* AP21 PAR64 AP22 AD[60] AP23 AD[57] AP24 AD[53] AP25 AD[49] AP26 AD[46] AP27 AD[42] AP28 AD[38] AP29 AD[35] AP30 VGG AP31 GND AP32 GND AP33 GND AP34 GND ® Mindspeed Technologies Mindspeed Proprietary and Confidential Introduction 27 ...

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... CX28500 Hardware Signals Description CX28500 is packaged × 35 mm, 580-pin BGA. The pin input/output functions are defined in Pin labels, signal names, I/O functions, and signal definitions are provided in always denoted with a trailing asterisk (*). Table 1-7. I/O Pin Types I/O I Input. High impedance, TTL. O Output. CMOS. ...

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... If in Motorola mode, then it should be pulled- up. t/s O When asserted, CX28500 acknowledges to the bus arbiter that the bus grant signal was detected and a bus cycle is sustained by CX28500 until this signal is deasserted. This is used in Motorola mode only. ® Mindspeed Technologies Mindspeed Proprietary and Confidential ...

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... If the serial port operates in channelized TSBUS mode, then TSTUFF assertion indicates that no data needs to be transmitted in the 8th time slot after the assertion of the TSTUFF. Note that while operating in channelized TSBUS mode, CX28500 requires the following: 1. The stuff status for each time slot to be presented at its TSTUFF input exactly eight time slots in advance of the actual time slot for which the stuff status applied ...

Page 46

... I/O t/s O Serial data latched out on active edge of transmit clock, TCLKx. If channel is unmapped to time slot, data bit is considered invalid and CX28500 outputs either three-state signal or logic 1 depending on TRITx bit field value in Table 6-36, TSIU Port Configuration with other drivers, this signal is three-stated until the detection of the first TSYNC pulse, and during COFA ...

Page 47

... Register and TSIU Time Slot Pointers Register) and the RPORT_TYPE or TPORT_TYPE value (RSIU Port Configuration Register and TSIU Port Configuration Register) specifying whether the serial port operates in channelized or unchannelized mode must be identically configured for both directions per serial port. Unexpected CX28500 behavior may be generated if this restriction is violated. ® Mindspeed Technologies ...

Page 48

... The final data cycle is indicated by the deassertion of FRAME*. For a non- burst, one-data-cycle bus cycle, this pin is only asserted for the address phase. t/s I/O CX28500 asserts this signal when it needs to perform a 64-bit transfer. This signal is used during PCI reset to inform the system that the PCI is 64-bits wide. ...

Page 49

... CX28500 drives REQ* to notify the PCI arbiter that it desires to master the bus. Every master in the system has its own REQ*. I The PCI bus arbiter asserts GNT* when CX28500 is free to take control of the bus, assert FRAME*, and execute a bus cycle. Every master in the system has its own GNT*. ...

Page 50

... Table 1-8. CX28500 Hardware Signal Definitions ( Pin Label Signal Name TCK JTAG Clock TRST* JTAG Enable TMS JTAG Mode Select TDO JTAG Data Output TDI JTAG Data Input TM[0] Test Mode TM[1] TM[2] VDD_c VDD_io VGG Input Tolerance GND No Connect No Connect FOOTNOTE: (1) While operating in TSBUS mode, there is no damage expected when sampling STBx twice, since the RCLKx and TCLKx are the same signals for a specific port ...

Page 51

... Serial Line Processing (SLP)—TSLP and RSLP for the transmit and receive directions • Direct Memory Access Controller (DMA) • Interrupt Controller (INTC) Figure 2-1 illustrates the different signal connection between the SIU and the host interface while the CX28500 is configured to operate in conventional or channelized TSBUS mode. Figure 2-1. Serial Interface Functional Block Diagram Rx Control Rx Data ...

Page 52

... RSIU translates the time slot to a channel number (using an internal map) and provides certain parameters that are needed by the RSLP to process the incoming data. Similar to the TSIU, for the TSBUS mode, one frame is defined as the STB strobe interval. 28500-DSH-002-C ® Mindspeed Technologies Mindspeed Proprietary and Confidential Internal Architecture 37 ...

Page 53

... Start to transmit data from the first time slot assigned to the logical channel • Generate pad fill between messages • Handle channel activation/deactivation • Handle COFA and under-run • Invert outgoing data • Handle subchanneling • Interrupts • BUFF, and EOM 28500-DSH-002-C ® Mindspeed Technologies Mindspeed Proprietary and Confidential Internal Architecture 38 ...

Page 54

... Of Message (EOM) conditions • Automatic polling of Buffer Descriptor • Complete Buffer Control • Buffer Pointer • Buffer Length • Ownership (Host/CX28500) • End Of Buffer Interrupt Mask (EOBIEN) • Poll/No poll Control • Self-service mechanism • Zero host intervention required • Support self-service for receive to transmit loopback • ...

Page 55

... The Interrupt Controller takes receive and transmit events/errors from RSIU, RSLP, RxDMA and TSIU, TSLP, and TxDMA respectively. The Interrupt Controller coordinates the transfer of internally queued descriptors to an interrupt queue in shared memory and coordinates notification of pending interrupts to the Host. 28500-DSH-002-C ® Mindspeed Technologies Mindspeed Proprietary and Confidential Internal Architecture 40 ...

Page 56

... Transfers data between the serial interface and shared memory over the PCI bus. • Stores configuration state information. CX28500 does not support Function 1. The access to the EBUS is performed via a service request command, which provides a better utilization of the PCI bus for local devices located on the EBUS. Figure 3-1 illustrates the Host interface block diagram ...

Page 57

... CX28500 supports Function 0 only. 3.1.2 PCI Bus Operations CX28500 behaves either as a PCI master or a PCI slave device at any time and switches between these modes as required during device operation. CX28500 supports only dword write transactions PCI slave, CX28500 responds to the following PCI bus operations: • ...

Page 58

... CX28500 master supporting fast back-to-back transactions, places the burden of avoiding contention on itself. While acting as a slave, CX28500 places the burden on all the potential targets master, CX28500 may remove the Idle state between transactions when it can guarantee that no contention occurs. This can be accomplished when the master’ ...

Page 59

... Valid values are 0 through 15. Accessing registers outside this range results in an all 0s value being returned on reads, and no action being taken on writes. The value of the signal lines AD[1:0] must be 00b for CX28500 to respond. If these bits are 0 and the IDSEL* signal line is asserted, then CX28500 responds to the configuration cycle. ...

Page 60

... PCI Master and Slave CX28500 is a single function PCI device that provides the necessary configuration space for a PCI bus controller to query and configure CX28500’s PCI interface. PCI configuration space consists of a device-independent header region (64 bytes) and a device-dependent header region (192 bytes). CX28500 provides the device-independent header section only ...

Page 61

... At reset, CX28500 sets the bits in this register to 0, meaning CX28500 is logically disconnected from the PCI bus for all cycle types except configuration read and configuration write cycles. Table 3-3. Register 1, Address 04h ( Bit Reset Name Field Value 31 Status ...

Page 62

... RO Wait cycle control. CX28500 does not support address stepping. RW Parity error response. This bit controls CX28500’s response to parity errors CX28500 takes normal action when a parity error is detected on a cycle as the target CX28500 ignores parity errors. RO VGA palette snoop. Unused. ...

Page 63

... The latency timer is an 8-bit value that specifies the maximum number of PCI clocks that CX28500 can keep the bus after starting the access cycle by asserting its FRAME*. The RO latency timer ensures that CX28500 has a minimum time slot for it to own the bus, but places an upper limit on how long it owns the bus. RO Unused. ® ...

Page 64

... Specifies how quickly CX28500 needs to gain access to the PCI bus. The value is specified in 0.25 µs increments and assumes a 33 MHz clock. A value of 0Fh means CX28500 needs to gain access to the PCI bus every 130 PCI clocks, expressed as 3.75 µs in this register. This value specifies, in 0.25 µs increments, the minimum burst period CX28500 needs. ...

Page 65

... CX28500 is disabled and responds only to PCI configuration cycles. 3.2.3 PCI Throughput and Latency Considerations For reference to PCI throughput and latency considerations see 3.2.4 Host Interface After a hardware reset, the PCI configuration space within CX28500 needs to be configured by the Host as follows: • Base address register • Fast back-to-back enable/disable • ...

Page 66

... Expansion Bus (EBUS) CX28500 provides access to a local bus interface on the CX28500 called the Expansion Bus (EBUS), which provides a Host processor to access any address in the peripheral memory space on the EBUS. Although EBUS utilization is optional, the most notable applications for the EBUS are the connections to peripheral devices (e.g., Bt8370/Bt8398 T1/E1 framers, CX28398 (Octal DS1/E1 framers), CX28314/CX28313 (multiplexer- demultiplexer DS1 to DS3 plus framer) that are local to CX28500’ ...

Page 67

... EBUS—Operational Mode 4.1.1 Initialization After reset and after the PCI configuration is completed, CX28500 provides the Host the ability to read and write peripheral devices located on the EBUS (refer to to instruct CX28500 to perform specific EBUS operations. CX28500 can perform bulk service request commands. ...

Page 68

... Offset When an EBUS_RD is issued, CX28500 executes a PCI bursted write of EBUS transactions and will store the data (EAD[31:0 internal buffer. When the EBUS transaction ends, CX28500 bursts the data over the PCI to the location specified by Shared Memory Pointer (Buffer Address). The EBE[3:0]* drives the programmed EBUS Byte Enabled (EBE) value set in the Access Control Field dword ...

Page 69

... Bus Access Interval CX28500 can be configured to wait a specified amount of time after it releases the EBUS and before it requests the EBUS a subsequent time. This is accomplished by specifying a value between 0 and 15 in the BLAPSE bit field in EBUS configuration register. The value specifies the additional ECLK periods CX28500 waits immediately after 28500-DSH-002-C ® ...

Page 70

... That is, a value of 0 specifies CX28500 will wait for one ECLK period, and a value of 15 specifies 16 ECLK periods. Disabling the ECLK signal output does not affect this wait mechanism. The bus grant signal (HLDA/BG*) is deasserted by the bus arbiter only after the bus request signal (HOLD/BR*) is deasserted by CX28500 ...

Page 71

... If BG* is found to be deasserted, CX28500 waits for the BG* signal to become asserted before continuing the EBUS operation BG* is found to be asserted, CX28500 continues with the EBUS access as it has control of the EBUS BGACK* is not asserted CX28500 assumes control of the EBUS by asserting BGACK*. ...

Page 72

... EAD[31:24] EAD[23:16] EAD[15:8] EAD[7:0] EAD[8:0] Data Addr Data Addr Bt8370 Bt8370 CS* CS* Device 0,4 Device 1,5 dev 0,4 Chip Select Logic ® Mindspeed Technologies Mindspeed Proprietary and Confidential Expansion Bus (EBUS) Figure 4-3 illustrates four Data Addr Data Addr Bt8370 Bt8370 CS* CS* Device 2,6 Device 3,7 500052_050 57 ...

Page 73

... Data Addr Data Addr Bt8370 Bt8370 CS* CS* dev 0 dev 1 dev 0, bank 0 Control dev 0, bank 1 dev 0, bank 2 dev 0, bank 3 ® Mindspeed Technologies Mindspeed Proprietary and Confidential Expansion Bus (EBUS Data Addr Data Addr Bt8370 Bt8370 CS* CS* dev 2 dev 3 500052_051 ...

Page 74

... The four devices are multiplexing the address in shared memory. The framer’s configuration software has to read the whole block of framers configuration before it starts demultiplexing data per device. Figure 4-6. EBUS Connection, Multiplexed Address/Data, 4 Framers, No Local MPU EBUS CX28500 28500-DSH-002-C Data Addr Data Addr Bt8370 ...

Page 75

... RSIU translates the time slot to a channel number (using an internal map) and provides certain parameters that are needed by the RSLP to process the incoming data. Similar to the TSIU, for the TSBUS mode, one frame is defined as the STB strobe interval. 28500-DSH-002-C ® Mindspeed Technologies Mindspeed Proprietary and Confidential 60 ...

Page 76

... Frame Synchronization Flywheel CX28500 utilizes the TSYNC and RSYNC signals to maintain a time-base, which keeps track of the active bit in the current time slot. The mechanism is referred to as the frame synchronization flywheel. The flywheel counts the number of bits per frame and automatically rolls over the bit count according to the programmed mode. The TSYNC or RSYNC input marks the first bit in the frame ...

Page 77

... OOF assertion on a specific time slot. For ROOF to be deasserted, CX28500 must detect at least one frame without any OOF’s. As ROOF is deasserted, CX28500 immediately restarts normal processing on all active channels. One to three time slots after deassertion ...

Page 78

... Frame Alignment CX28500 utilizes the TSYNC and RSYNC signals to maintain a timebase that keeps track of the active bit in the current time slot. The mechanism is referred to as the frame synchronization flywheel. The flywheel counts the number of bits per frame and automatically rolls over the bit count according to the programmed mode. The TSYNC or RSYNC inputs mark the first bit in the frame ...

Page 79

... fetched, CX28500 checks the owner bit to verify whether the buffer is available for CX28500. If the owner bit indicates that the Host still owns the buffer, the Host has not prepared the data for processing in the data buffers ...

Page 80

... The RPOLLTH or TPOLLTH bit fields in RSIU Port Configuration register and TSIU Port Configuration register, bit field specifies how often CX28500 checks the owner bit in a Host-owned Buffer Descriptor. The values correspond 16, 64, 128, and 256 frame periods. NOTE: ...

Page 81

... TSBUS Frame Synchronization Flywheel The CX28500’s TSTB signal maintains a time-base that keeps track of the active bit in the current time slot. The mechanism is referred to as the frame synchronization flywheel. The flywheel counts the number of bits per frame and automatically rolls over the bit count according to the programmed mode. The TSTB input marks the first bit in the frame ...

Page 82

... TSBUS Frame Alignment The serial data stream that CX28500 can manage consists of either packetized data or unpacketized data. CX28500 supports two types of data-stream modes: HDLC and Transparent. In Transparent mode, message processing for every channel begins in the time slot marked as the first time slot in the channel’ ...

Page 83

... TSTUFF advance is fixed at eight time slots even though the number of time slots within a frame might vary. For the receive direction, CX28500 requires the stuff status for each time slot to be presented at its RSTUFF input on the current time slot for which the stuff is applied. ...

Page 84

... Examples of the overhead TSBUS operates at a data rate of 12.96 Mbps. It carries PDH, or SDH overhead communication channels and it carries the data monitoring and data configuration for the device that communicates through TSBUS interface with CX28500. The data on the overhead TSBUS is framed and consists of 84 time slots. ...

Page 85

... CX28500 devices on the bus to claim these access cycles. As CX28500's address ranges are accessed, CX28500 behaves as a PCI slave device while data is being read or written by the Host. CX28500 responds to all access cycles where the upper 12 bits of a PCI address match the upper 12 bits of CX28500’s Base Address register (see ...

Page 86

... Port Alive, the Interrupt Status Descriptor, the Interrupt Queue Pointer, the Interrupt Queue Length, the Service Request Length, the Service Request Pointer, and the Soft Reset registers specified in CX28500’s Register Map. When the Host writes directly into a corresponding register, CX28500 behaves as a PCI slave while this write is performed. ...

Page 87

... It is critically important that upon channel activation, shared memory and internal registers must be initialized, valid, and available to CX28500. CX28500 uses the information within the shared memory descriptors to transfer data between the serial interface and shared memory. CX28500 assumes the information is valid once a channel is activated. ...

Page 88

... Since the Host cannot modify the Service Request Length register while it is non-0, the setting of this register to all 1s by CX28500 effectively prevents the Host from making additional service requests that could interfere with its internal initialization. When CX28500 is finished with the internal initialization, it clears this field to 0 ...

Page 89

... The number of dwords copied is specified in the LENGTH bit field. The user needs to instruct CX28500 to perform the correct number of reads so that when data is written in shared memory, no data overlapping occurs. The Service Request Descriptor used for this command is Device Configuration Descriptor ...

Page 90

... EOM indication is received. When an EOM indication is received (or if there is no active transfer), CX28500 fetches a new head pointer buffer descriptor for this channel from shared memory (actually from the Transmit Head Pointer Table (THPT) or Receive Head Pointer Table (RHPT)) ...

Page 91

... Register Map Address to the specified register that needs to be configured. This address is a dword-aligned address, meaning the 2 LSB must equal to 0. Bits [18:2] contain the map address while bits [31:19] are reserved. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Memory Organization Bit 0 (1) ...

Page 92

... The address of shared memory EBUS base address, where the configuration of local devices exists. This pointer is dword-aligned, hence bits [1:0] must equal — EBUS base (byte-aligned) address for an EBUS transaction. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Memory Organization Bit 0 EBUS Byte Enable Length[13:0] [17:14] ...

Page 93

... The command is for the Transmit channel. — Channel number. This field is interpreted as a channel number for the CH_ACT, CH_DEACT and CH_JUMP command. The field is interpreted as reserved for the NOP command. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Memory Organization Bit 0 Direction[10] Channel[9:0] ...

Page 94

... Configuration for that specific port is allowed. Type 0 RO This register controls the access to the Transmit Port Configuration register. If one of 32 bits is set to 1, then the Transmit Port Configuration for that specific port is allowed. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Memory Organization Tables 6-12 Description Description 79 ...

Page 95

... Soft Chip Reset Register Any write of any value to a Soft Chip Reset (SCR) generates a soft reset for CX28500. An SCR write affects CX28500 exactly as PCI Reset, except that the PCI block is not reset. No PCI configuration is performed after a SCR. 6.2.4 General PCI Note While addressing CX28500 in slave mode, every PCI access must have all four byte enables active. Any PCI accesses without all four bytes enabled is treated as if all four byte enables were inactive ...

Page 96

... To switch interrupt queues, first write IQLEN. Next, write the base address of the new interrupt queue into IQPTR in the Interrupt Queue Pointer. Finally, write the new interrupt queue length into IQLEN. Note(s): Since CX28500 must work with 64-bit alignment, there must be an even number of entries in the buffer. 6.3.1.1 Interrupt Descriptors The interrupt descriptor describes the format of data transferred into the queue ...

Page 97

... Only one bit is overwritten and the integrity of the original descriptor is maintained. The CX28500 has two types of interrupt descriptor. One is the DMA Interrupt Descriptor, and the other is the Non- DMA Interrupt Descriptor. The following items describe the errors/events reported in the DMA Interrupt Descriptor: • ...

Page 98

... Receive/ Transmit Buffer Descriptor. The EOB interrupt reports the correct number of received transmitted bytes in BLEN field. 1: RxONR/TxONR–Generated when the next Buffer Descriptor is not available to CX28500 when expected, the NP bit field in the buffer descriptor is set and the DMA is in the middle of a message, and the ownership interrupt is enabled (bit field ONR in RDMA Channel Configuration register or TDMA Channel Configuration register) ...

Page 99

... Interrupt Lost. Generated when internal interrupt queue is full and more interrupt conditions are detected. Because CX28500 cannot store the newest interrupt descriptors, it discards the new interrupts and overwrites this bit in the last interrupt in an internal queue prior to that interrupt being transferred out to shared memory ...

Page 100

... Non-DMA Interrupt Descriptors Format ( Bit Field Name Value 41 RxBUFF/ — Receive or Transmit Buffer Errors TxBUFF The data is lost. CX28500 has no place to read or write data internally. If reported as TxBUFF, the internal buffer underruns. If reported as RxBUFF, the internal buffer overflows. 40:38 RSVD — Reserved. 37 RxSHT/ — ...

Page 101

... CX28500, either from another PCI agent that writes into CX28500 registers or from CX28500 that reads data from shared memory. This error is specific to the data phase of a PCI transfer while CX28500 is receiving data. PCI system error signal, SERR*, is ignored by CX28500. To mask the PERR interrupt— ...

Page 102

... Quadwords of queue space. This sets the lower limit for the queue size. The Host must store the pointer to the queue and the length in Quadwords of the queue in CX28500 within the Interrupt Queue Descriptor registers. Issuing the appropriate Host service to CX28500 can do this. As CX28500 takes in the new values, it automatically resets the controller logic as indicated above ...

Page 103

... Descriptor sent to the Host. If the interrupt is not masked, CX28500 generates a descriptor and stores it internally prior to transferring it to the Interrupt Queue in shared memory. The internal queue is capable of holding 512 descriptors while CX28500 arbitrates to master the PCI bus and transfer the descriptors into the Interrupt Queue in shared memory. ...

Page 104

... Status Buffer Descriptor (i.e., the data pointer the Tx direction, CX28500 assumes that the field PADCOUNT in the Buffer Descriptor is 0. This enables the Host to write any value that helps to better handle buffers circulation into this location knowing that CX28500 does not use PADCOUNT and preserve this value in the Status Buffer Descriptor ...

Page 105

... CX28500 to ignore the PCI configuration settings and execute fast back-to-back transactions when appropriate. The Host can set this bit only if CX28500 is always accessing the same target which is capable of fast back to back transactions. This is not a violation of the PCI specification, rather implementation of allowed behavior ...

Page 106

... This wait ensures that all the bus grant signals driven by the bus arbiter have sufficient time to be deasserted as a result of bus request signals being deasserted by CX28500. Expansion Bus Data Duration. CX28500 extends the duration of valid data bits during an EBUS data phase to ELAPSE+1 number of ECLK periods. The control lines RD* and WR* (Intel) or DS* and R/ WR* (Motorola) indicate the data bits have had the desired setup time. ® ...

Page 107

... The Receive Channel Configuration register contains configuration bits applying to the logical channels within CX28500. There are 1024 such registers, one for each channel. The RSLP Channel Configuration Descriptor configures aspects of the channel common to all messages passing through the channel. One descriptor exists for each logical channel direction ...

Page 108

... There is one RDMA Buffer Allocation register for each logical channel (i.e., 1024 channels). CX28500’s internal Rx memory is a 32-KB dual-port RAM, which can be split into 1024 parts, one part for each channel. The allocation granularity is two dwords. For each active channel it is required to specify the following: • ...

Page 109

... Host memory and this buffer is Host-owned and NP bit field Error Interrupt disabled. 1 Error Interrupt enabled. Interrupt generated when End Of Message detected and error occurred (such as: too-long message, FCS error, and message alignment error or abort condition). ® Mindspeed Technologies Mindspeed Proprietary and Confidential Memory Organization Description Description 94 ...

Page 110

... FOOTNOTE: (1) The normal mode of operation of the CX28500 is to overwrite the Rx Buffer Descriptor with Rx Buffer Status Descriptor. This bit is used to inhibit this behavior, so that when it is set, the Rx Buffer Descriptor is not overwritten and the Host must rely on interrupts to find out when the CX28500 relinquishes ownership of the buffers. ...

Page 111

... RSIU Time Slot Pointer Allocation Register There is one RSIU Time Slot Pointer Allocation Descriptor for each of CX28500’s 32 serial ports. This register sets the start and end time slot address for the specific configured port. The difference between the configured end and start address specifies the number of time slots allocated for the specified serial port ...

Page 112

... In the case of unchannelized mode (i.e., the RPORT_TYPE field in RSIU Port Configuration register is programmed to 0), CX28500 assumes that only one entry (the one pointed to by STARTAD) is used for this port. This frees the ENDAD pointer to point to any location in the RSIU time slot memory. The differences in these pointers now define the number of time slots to count for polling purposes as described in section Descriptor Polling ...

Page 113

... OOF Message Processing Enabled. When OOF condition is detected, continue processing incoming data. SIU should not report about the OOF. 1 OOF Message Processing Disabled. 0 Out Of Frame/Frame Recovery Interrupt Disabled. 1 Out Of Frame/Frame Recovery Interrupt Enabled. If OOF/FREC is detected, generate Interrupt indicating OOF/FREC. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Memory Organization Description 98 ...

Page 114

... OOF recovery interrupt when the OOF condition ends OOFABT is 1 and OOFIEN is 0: CX28500 as the case of both 1s except that no interrupt is generated OOFIEN is 1 but OOFABT is 0: This is the case where the ROOF pin is used as a general purpose interrupt pin ...

Page 115

... TSLP Channel Status Register The TSLP Channel Status register, defined in It provides information from the TSLP block regarding the channel state and status. There is one TSLP Channel status register for each of CX28500’s channels (i.e., 1024 registers). Table 6-30. TSLP Channel Status Register ...

Page 116

... The Buffer Allocation register configures the internal receive memory. There is one TDMA Buffer Allocation register for each logical channel (i.e., 1024 channel). CX28500’s internal Tx memory is a 32-KB dual RAM, which can be split into 1024 parts, one part for each channel. The allocation granularity is two dword. For each active channel it is required to specify the following: • ...

Page 117

... Starting address of internal channel data buffer. Value 0 Reserved. 0 End Of Command Execution Interrupt disabled. 1 End Of Command Execution Interrupt enabled. Interrupt generated when a command (Activate, Deactivate or Jump) execution was completed. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Memory Organization Description Description 102 ...

Page 118

... FOOTNOTE: (1) The normal mode of operation of the CX28500 is to overwrite the Tx Buffer Descriptor with Tx Buffer Status Descriptor. This bit is used to inhibit this behavior, so that when it is set, the Tx Buffer Descriptor is not overwritten and the Host must rely on interrupts to find out when the CX28500 relinquishes ownership of the buffers. ...

Page 119

... The timeslot map registers have no default values and may be active after reset, so they must be configured before activating the port. 6.7.6 TSIU Time Slot Pointer Assignment Register There is one TSIU Time Slot Pointer Allocation Descriptor for each of CX28500’s 32 serial ports. This register, defined in Table 6-35, sets the start and end time slot address for the specific configured port ...

Page 120

... In the case of unchannelized mode (i.e., the PORTTYP field in TSIU Port Configuration register is programmed to 0), CX28500 assumes that only one entry (the one pointed to by STARTAD) is used for this port. This frees the ENDAD pointer to point to any location in the TSIU time slot memory. The differences in these pointers now define the number of time slots to count for polling purposes as described in section Descriptor Polling ...

Page 121

... Time Slot Map, the transmitter outputs a logic 1 on the output data signal. 1 Transmit Three-state Enabled. When a port is enabled, but a time slot within the port is not mapped via the Time Slot Map, the transmitter three-states the output data signal. 28500-DSH-002-C Description ® Mindspeed Technologies Mindspeed Proprietary and Confidential Memory Organization 106 ...

Page 122

... HDLC, transparent, etc.). The polling mechanism in the CX28500 uses these markings as triggering points. When configured correctly, CX28500 polls on a channel once at the selected poll throttle rate instead of polling at every time slot allocated to that channel the case of hyperchannels ...

Page 123

... Receive and Transmit Data Structures Figures 6-2 and 6-3 illustrate the receive and transmit data structures used for data communication between CX28500 and the Host. Figure 6-2. Transmit Data Structures Transmit Base Address Head Pointer (TBAHP) Base Address Head Pointer (1) (BAHP) Transmit Internal Message ...

Page 124

... Descriptor (BSD) (2) MDHP (Ch #I) BSD BSD (2) MDHP 1023 Receive Message Descriptor Table (RMDT Ch #I) BSD BSD BSD Shared Memory ® Mindspeed Technologies Mindspeed Proprietary and Confidential Memory Organization Data 0 Buffer (3) Data 4095 Buffer Data 0 Buffer Data 4095 Buffer 500052_058 109 ...

Page 125

... Transmit Internal Message Processing Table (TIMPT) For each channel’s message descriptor (MD) table, CX28500 maintains a pointer to its first MD copied from the head pointer table and a pointer (actually the offset from the starting address of the current MD being processed). The length of Transmit Message Descriptor table is given by the fact that the 12-bit field in Transmit Internal Message Processing Table (TIMPT) ...

Page 126

... Receive Internal Message Processing Table (RIMPT) For each message descriptor (MD) table, CX28500 maintains a pointer to its first MD copied from the head pointer table and a pointer (actually the offset from the starting address of the current MD being processed). The length of Receive Message Descriptor table is given by the fact that the 12-bit field in Receive Internal Message Processing Table (RIMPT) ...

Page 127

... After CX28500 processes the data buffer, it grants the ownership back to the Host. If the ONR-bit indicates that CX28500 does not own the next buffer and (polling is not enabled) and in mid-message, then this is an error condition. CX28500 generates ONR interrupt and all the DMA handling is ...

Page 128

... Buffer Descriptors The Buffer Descriptor (BD) resides in the shared memory and is fetched by CX28500 each time a new data buffer is required. All Buffer Descriptors include the following fields: • Owner Indicator Bit (ONR) • ...

Page 129

... BLEN[13:0] — FOOTNOTE: (1) IC field is processed and used by CX28500 only when EOM is set (i.e., only in the last buffer descriptor of a message). (2) PADCNT field is processed and used by CX28500 only when EOM is set (i.e., only in the last buffer descriptor of a message). (3) The combination of BLEN = 0 and EOM = 0 in the middle of a message is not allowed. ...

Page 130

... When operating in normal mode (i.e., not Preserve Channel Mode as indicated by bit PCHMODE in Global Configuration Descriptor) this field is Reserved. When operating in Preserve Channel Mode, this field is used by CX28500 to transfer the least significant 8 bits of the channel number. The most significant bits are transferred to the data pointer. ...

Page 131

... PADCOUNT. PADCNT indicates the minimum number of idle codes to be inserted between the closing flags and the next opening flag (7Eh). If PADCNT = 2 and for example, CX28500 outputs the bit pattern 7Eh..FFh..FFh..7Eh. There is no indication by CX28500 if more than PADCNT number of idle codes are inserted ...

Page 132

... While operating in Preserve Channel Mode (i.e., bit PCHMODE in Global Configuration Descriptor is set), CX28500 transfers in DATAPTR[1:0] the two MSBs of the channel number and uses bit DATAPTR[2] to signal if this buffer is the first buffer of a received message (i.e., DATAPTR[2] is set) or not (i.e., DATAPTR[2] is clear). This is illustrated in Table 6-45 ...

Page 133

... SOM_STATUS 1:0 CHAN_MSBs — 28500-DSH-002-C Write back DATAPTR value. 0 Start of message status: not start. 1 Start of message status: start of message contained in current buffer. Two most significant bits of the logical channel number CHAN[9:8]. ® Mindspeed Technologies Mindspeed Proprietary and Confidential Memory Organization Description 118 ...

Page 134

... Hard PCI Reset The PCI reset is the most thorough level of reset in CX28500. All subsystems enter into their initial states, including the PCI interface. PCI reset is accomplished by asserting the PCI signal, PRST*. The PRST* signal is an asynchronous signal on the PCI bus. The reset signal can be activated in several ways. ...

Page 135

... The effects of a PCI reset signal within CX28500 takes ten PCI clock cycles to complete after deasserting the reset signal. After this time, the Host can communicate with CX28500 using the PCI configuration cycles. After the PCI configuration, the device is not ready to start communication with the Host via service request mechanism until the SRQ_LEN bit field in Service Request register is set to 0 ...

Page 136

... After PCI configuration is complete, a set of hierarchical configuration sequences must be executed to begin operation at the channel level. The Service Request mechanism is the main communication channel between CX28500 and the Host used to configure CX28500’s registers, read status registers, execute transactions over the EBUS, and activate ports and channels ...

Page 137

... Typical Initialization Procedure This section depicts a typical initialization procedure. 1. PCI Configuration 2. PCI Reset or Soft Chip Reset (a Soft Chip Reset is performed by a direct write to the CX28500 register map— in the Soft Chip Reset register) NOTE: After performing a Soft Chip Reset not necessary to reconfigure the PCI. ...

Page 138

... Length register by performing a direct write. [13.4]. If other Service Request Table is required, the Host must poll the Service Request Length register by performing a direct read and check the SRQ_LEN field. If this field is not 0, then CX28500 did not complete the execution of the last Service Request Table. The number written in the SRQ_LEN indicates how many Configuration Write Commands (i ...

Page 139

... CX28500 checks bit field OWNER and NP in Buffer Descriptor. If OWNER = 1, CX28500 is buffer owner step 4. If OWNER = 0, CX28500 is not the buffer owner and TDMA buffer processing for this channel is temporarily suspended. There are several ways of TDMA to exit the channel suspended state: a ...

Page 140

... Head Pointer and stores in internal channel descriptor memory. 4. CX28500 checks bit field OWNER and NP in Receive Buffer Descriptor. If OWNER = 0, CX28500 is the buffer owner step 5. If OWNER = 1, CX28500 is not the buffer owner and RDMA buffer processing for this channel is temporarily suspended. There are several ways for RDMA to exit the channel suspend state: a ...

Page 141

... CX28500 writes DATA from its FIFO to the memory buffer until either an End Of Message (EOM) is stored or the entire memory buffer (BLEN) is filled. 6. CX28500 checks INHTBSD bit field in Buffer Descriptor with a Buffer Status Descriptor), it overwrites the Receive Buffer Descriptor. If the message ended (i.e., EOM is set in the Receive Buffer Status Descriptor step 7. If the EOM is not set in Receive Buffer Status, it might generate an EOB interrupt depending on EOBIEN bit setting in the Receive Buffer Descriptor ...

Page 142

... CH_JMP service request was performed, and the next Head Pointer was read. However, this does not mean that CX28500 starts working on the new message descriptors table pointed by the new Head Pointer immediately. Channel jump takes effect after an End Of Message (EOM) is fetched from or stored to memory buffer or while the channel is in suspended state ...

Page 143

... If CX28500 suspends a channel’s operation, the Host must perform a channel reactivation by issuing either a Channel Activation Service Request or a Channel Jump Service Request. This is referred to as “requiring reactivation.” On the receiving side one scenario that would suspend a channel is when a message descriptor is Host owned and encountered. On the transmission side, several occurrences of COFA’ ...

Page 144

... Transmit channel has been activated by a Host service request. • If not in unchannelized mode, then CX28500 waits until the first detection of a sync pulse or strobe to get out of three-state. If TxENBL bit is set to 0 (transmit port disabled), the serial data output signal is placed in high-impedance three- state. If TxENBL = 1 (port enabled) and a time slot is disabled, the corresponding time slot’ ...

Page 145

... An HDLC message is always bounded by this flag at the beginning and the end of the message. CX28500 supports receiving a shared flag where the closing flag of one message can act as the opening of the next message. CX28500 also supports receiving a shared-zero bit between two flags—that is, the last zero bit of one flag is used as the first zero bit of the next flag ...

Page 146

... Change To Abort Code interrupt is equal to 14 consecutive ones. In the transmission direction, an ABORT code’s handling is depended on what the user tells CX28500 to do. An ABORT code could just abort the transmission of the current message can mean aborting the current message transmission and then starting transmitting the next message exists ...

Page 147

... Ending a Message with an Abort or Sending an Abort Sequence If BLEN = 0 in any transmit buffer descriptor, CX28500 interprets request to end an in-progress message with the abort sequence. If the previous buffer descriptor (before the BLEN = 0 buffer) contained an End-Of- Message (EOM) indication, the abort request is simply ignored and CX28500 moves on to the next message descriptor ...

Page 148

... Receive events are informational in nature and do not require channel recovery actions. 8.2.7.1 End Of Buffer [EOB] Reason: • One message is split across multiple shared memory buffers. CX28500 reached the end of a buffer by servicing (writing) the number of bytes equal to BLEN specified in the Receive Buffer Descriptor. Effects: • EOB Interrupt (if EOBIEN = 1 in Receive Buffer Descriptor). ...

Page 149

... RSLP and RDMA continue normal processing. 8.2.7.4 Change to Idle Code (CHIC) Reason: • RSLP detects received data changed to flag (7Eh) octets. CX28500 requires detection of three consecutive flags and the previous idle code is all 1s before a CHIC event is generated. Effects: • CHIC interrupt (if IDLEIEN = 1 in • ...

Page 150

... Transmit Underrun [BUFF] CX28500 needs to send more data toward the TSIU for an in-progress transmit message, but the internal channel FIFO is empty. Reasons: • Degradation of the Host subsystem or application software. • Buffer descriptor containing the continuation of a message is Host-owned. • PCI bus congestion. ...

Page 151

... Receive Errors Receive errors are service-affecting, but do not require a corrective action by the Host to resume normal processing, except when CX28500 fetches a HOST owned message buffer descriptor. Then a jump service request is required to resume normal processing. NOTE: In all the cases where a message is received and its buffer descriptor is closed with any of the errors listed below, the ABORT field of the receive status descriptor is set to non-zero ...

Page 152

... NOTE: Since CX28500 completely separates the two processes of storing data in shared memory buffers and receiving data from the serial interface irrelevant to CX28500 how the overflow condition was created specific, there is no distinction between a BUFF error created due to a Host-owned buffer descriptor or due to a latency-induced full FIFO condition ...

Page 153

... Channel Level Recovery Actions: • None required. 8.2.9.4 Frame Check Sequence (FCS) Error In this case, the Frame Check Sequence (FCS) which CX28500 calculated for the received HDLC message does not match the FCS located within the message. Reason: • Bit errors during transmission. ...

Page 154

... The received HDLC message length is determined to be greater than the maximum allowable message size per the MAXSEL bit field in Section 6.6.8. Reason: • Incorrect message transmission from distant end. Effects: 28500-DSH-002-C Section 6.6.4 Section 6.6.4 ® Mindspeed Technologies Mindspeed Proprietary and Confidential Basic Operations Section 6.6.4 and Section 6.7.4) and Section 6.7.4). Section 6.6.4 and Section 6 ...

Page 155

... Channel Level Recovery Actions: • None required. 8.3 Transparent Mode CX28500 supports a completely transparent mode where no distinction is made between information and non- information bits in the channel bit stream. This mode is assigned on a per-channel and per-direction basis by the PROTOCOL bit field in Section 6.6.2 28500-DSH-002-C Section 6 ...

Page 156

... When the ABORT field is non-zero in any CX28500-owned transmit buffer descriptor, CX28500 interprets this as a request to end an in-progress message with the abort sequence. Abort sequence for Transparent mode is defined sequence of all 1s. The abort sequence is terminated only when a new CX28500-owned message descriptor with a non-zero BLEN becomes available. In this case, CX28500 resynchronizes the start of the next message transmission to the time slot marked as the first time slot on that channel. If ABORT ≠ ...

Page 157

... TxEOB interrupt (if EOBIEN = 1 in Transmit Buffer Descriptor). • CX28500 continues with normal message processing. If the TDMA does not get more data from shared memory before the internal channel FIFO becomes empty and the TSLP needs to output another data bit, TSLP generates an underflow error. ...

Page 158

... TSLP), but eventually the TDMA stops servicing this channel because the TSLP has stopped sending data. Channel Level Recovery Actions: • Transmit channel complete reactivation is required. 28500-DSH-002-C Section 6.6.5) with the appropriate RxERR status. Table 6-28, RSIU Port Configuration Table 6-28, RSIU Port Configuration Section 6.7.2). ® Mindspeed Technologies Mindspeed Proprietary and Confidential Basic Operations Register). Register). 143 ...

Page 159

... Receive Overflow [BUFF] Same as HDLC mode. Reasons: • Degradation of Host subsystem performance. • Shortage of shared memory buffers. The receive buffer CX28500 needs to fill is presently Host-owned. • PCI bus congestion. Effects: • RxBUFF Interrupt (if BUFFIEN = 1 in • Data received during an overflow condition is discarded. ...

Page 160

... RDMA is not affected and continues shared memory buffer processing. Channel Level Recovery Actions: • None required. 28500-DSH-002-C Section 6.6.4 Table 6-28, RSIU Port Configuration Table 6-28, RSIU Port Configuration ® Mindspeed Technologies Mindspeed Proprietary and Confidential Basic Operations and Section 6.7.4). The only exception to Section 8.3.5.4. Register). When the COFA Register) ...

Page 161

... RSLP restarts channel operation as soon as the COFA condition is recovered and the channel reaches its first assigned time slot. • RDMA is not affected and continues shared memory buffer processing. Notice that no shared memory buffer descriptors are consumed. Channel Level Recovery Actions: • None required. 28500-DSH-002-C Section 6.6.2). ® Mindspeed Technologies Mindspeed Proprietary and Confidential Basic Operations 146 ...

Page 162

... The OWNER bit field in the buffer descriptor is set to 0. For the transmitter, this means the buffer is owned by the Host. For the receiver, this means the buffer is owned by CX28500. 5. The NP bit field in the transmit buffer descriptor is set to 0. This allows the CX28500 to poll the OWNER bit field of the buffer descriptors. ...

Page 163

... Buffer Descriptor Table to return the BLEN fields to the original value (be careful, though, not to overwrite the BLEN field of a buffer that the transmitter has not yet begun sending). 28500-DSH-002-C ® Mindspeed Technologies Mindspeed Proprietary and Confidential Self-Servicing Buffers 148 ...

Page 164

... VDD_io –0.5 VGG VDD_io–0.5 V –1 –10 i Latchup — Latchup — T – – — vsol ® Mindspeed Technologies Mindspeed Proprietary and Confidential Value Unit Maximum 3.3 V 4.6 V 6.0 V VGG + 0.3 V (not exceeding 6V 300 mA 150 mA 125 °C 125 °C 220 ° ...

Page 165

... IDD_c IDD_io P d Table 10-4. Symbol ® Mindspeed Technologies Mindspeed Proprietary and Confidential Value Unit Maximum 2.375 2.625 3.135 3.465 5.25 –40 +85 2.0 VGG + 0.3 0 0.8 — 400 — 4 — 85 — 1 — 0.3 (2) — 3.7 Value Units 2 ...

Page 166

... Overview This section defines the timing and switching characteristics of CX28500. The major subsystems include the Host interface, the expansion bus interface, and the serial interface. The Host interface is Peripheral Component Interface (PCI) compliant. For other references to PCI, see the PCI Local Bus Specification, Revision 2.1, June 1, 1995. The expansion bus and serial bus interfaces are similar to the Host interface timing characteristics ...

Page 167

... FOOTNOTE: (1) CX28500 works with any clock frequency between DC and 66 MHz, nominally. The clock frequency may be changed at any time during operation of the system as long as clock edges remain monotonic, and minimum cycle and high and low times are not violated. The clock may only be stopped in a low state. ...

Page 168

... Parameter (1) ( and V ). Timing parameters must be met with no more overdrive than this ® Mindspeed Technologies Mindspeed Proprietary and Confidential Max Units — ms µs — — Max Min Max Units 33 MHz 66 MHz 66 MHz ...

Page 169

... Input 28500-DSH-002-C Electrical and Mechanical Specification V test T val V test (3.3 V signaling) output current ≤ leakage current off inputs V V test valid V tl ® Mindspeed Technologies Mindspeed Proprietary and Confidential 500052_060 max test 500052_061 154 ...

Page 170

... Expansion Bus (EBUS) Timing and Switching Characteristics The EBUS timing is derived directly from the PCI clock (PCLK) input into CX28500. The EBUS clock can have the same frequency as the PCI clock can have half the frequency of the PCI clock. This option is configured in the EBUS Configuration register. Please see Table 10-9 ...

Page 171

... Figure 10-6. EBUS Input Timing Waveform ECLK Input 28500-DSH-002-C Electrical and Mechanical Specification Parameter 2) V test T val V test V test test V tl ® Mindspeed Technologies Mindspeed Proprietary and Confidential Value Units 0.6 VDD_io V 0.2 VDD_io V 0.4 VDD_io V 0.4 VDD_io V 1.5 V/ 500052_080 max ...

Page 172

... BLAPSE inserts a variable number of ECLK cycles to extend HOLD deassertion interval until the next bus request. 11. The address line A31 must be asserted in all transactions. 28500-DSH-002-C Electrical and Mechanical Specification (11) Address Data Byte Enables from EBUS Configuration Descriptor ALAPSE = 0 ELAPSE = 0 ® Mindspeed Technologies Mindspeed Proprietary and Confidential BLAPSE = 0 500052_067 157 ...

Page 173

... BLAPSE inserts a variable number of ECLK cycles to extend BR* deassertion interval until the next bus request. 11. The address line A31 must be asserted in all transactions. 28500-DSH-002-C Electrical and Mechanical Specification (11) Address Data Byte Enables from EBUS Configuration Descriptor ALAPSE = 0 ELAPSE = 0 ® Mindspeed Technologies Mindspeed Proprietary and Confidential BLAPSE = 0 500052_068 158 ...

Page 174

... Data Hold Time for HSSI ports (0–5) NOTES: 1. Parameters were characterized with C load = Output Delay 3. Input Signals 28500-DSH-002-C Electrical and Mechanical Specification Parameter 1 Parameter ® Mindspeed Technologies Mindspeed Proprietary and Confidential Min Max Units DC 52 MHz — — — — ...

Page 175

... Electrical and Mechanical Specification Parameter (1) ( test test test test test V tl ® Mindspeed Technologies Mindspeed Proprietary and Confidential Value Units 0.6 VDD_io V 0.2 VDD_io V 0.4 VDD_io V 0.4 VDD_io V 1.5 V/ max test V max 500052_07 160 ...

Page 176

... Figure 10-11. Serial Interface Data Delay Output Waveform TCLK TDAT (rising) TDAT (falling) 28500-DSH-002-C Electrical and Mechanical Specification V V test test T val test val test V tl ® Mindspeed Technologies Mindspeed Proprietary and Confidential max test V V max test 500052_071 161 ...

Page 177

... One frame of 193 bits occurs every 125 µs (1.544 MHz). 2. RSYNC and TSYNC must be asserted for a minimum of 1 CLK period. 3. CX28500 can be configured to sample RSYNC, TSYNC, RDAT, and TDAT on either a rising or falling clock edge independently of any other signal sampling configuration. 4. Relationships between the various configurations of active edges for the synchronization signal and the data signal are shown using a common clock signal for receive and transmit operations ...

Page 178

... MHz). 4. RSYNC and TSYNC must be asserted for a minimum of 1 CLK period. 5. CX28500 can be configured to sample RSYNC, TSYNC, RDAT, and TDAT on either a rising or falling clock edge independently of any other signal sampling configuration. 6. Relationships between the various configurations of active edges for the synchronization signal and the data signal are shown using a common clock signal for receive and transmit operations ...

Page 179

... Also applies to functional outputs for the EXTEST instruction. GENERAL NOTE: Figure 10-14. JTAG Interface Timing TDO 7 TCK 3 TDI TMS 28500-DSH-002-C Electrical and Mechanical Specification Parameter (1) (1) Parameter ® Mindspeed Technologies Mindspeed Proprietary and Confidential Minimum Maximum Units 80 — — — — ns Minimum Maximum Units 0 — ...

Page 180

... Package Thermal Specification Table 10-17. CX28500 Package Thermal Resistance Characteristics Package Mounting Conditions 580-pin TBGA Board-Mounted GENERAL NOTE: 1. LFM-linear feet per minute. 2. LMS-linear meters per second. 3. Junction to case temperature (°C): Tjc =Tac + (θja x Pd). Tjc = θ (measured) + Tac (measured) Where Tjc = Junction Temperature (see θ ...

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... A – 10 – B – DETAIL B (4 Places) g REF. 00. 00. ccc C – C – aaa C 6 ® Mindspeed Technologies Mindspeed Proprietary and Confidential ...

Page 182

... A transmitter Underflow (TxBUFF) is defined as the condition that exists when an output FIFO for a specific channel is emptied before transmission of a complete HDLC frame. A receiver Overflow (RxBUFF) is caused when CX28500 does not service a channel in time, which in turn is caused by either excessive PCI bus latency or other channel demands on the PCI. An Overflow is defined as the condition that exists when the input FIFO for a specific channel is completely full and that channel receives more input data ...

Page 183

... The PCI clock frequency is either MHz. • The Host causes no bottleneck in the operation of CX28500 and Host access latency (TRDY delay) is considered to be zero. Hence, this model also assumes that no PCI read transaction is ever retried due to target unavailability and the PCI bridge FIFO is large enough to accept continuous CX28500 transactions without becoming full. • ...

Page 184

... When dealing with received messages, the full set of PCI transactions processed by the DMA controller, per channel follows: • Read BD: CX28500 performs a burst read of 2 dwords from Host memory. This transaction takes ( cycles during 32-bit mode cycles during 64-bit mode. • ...

Page 185

... Host memory and is transferred to that channel’s SLP buffer by the DMA worst when its buffer is empty (BuffLen – Thr ) ----- - ch- 28500-DSH-002-C CX28500 PCI Bus Latency and Utilization Analysis ∑ ( • • 2 Read BD Read DATA 2 Write STATUS + + 64 ⎛ ⎛ ...

Page 186

... A.10 PCI Bus Utilization PCI bus utilization is defined to be the ratio of the amount of time CX28500 uses the bus to the total amount of time that could be utilized by all components on the bus, including the Host. Utilization is calculated by comparing the time required to transfer one bit of receive and one bit of transmit information across the PCI and the time required to fill one bit of internal buffer space ...

Page 187

... Amount of data transferred > Amount of data transferred in/out of the PCI during L same time 2. PCI bus utilization allows an estimation of the number of CX28500 devices that can share one PCI bus. However, the relationship between utilization and the number of CX28500 devices is not linear. 3. The amount of data filled during the usage of spare cycles plus the amount of data already in the buffer can be used as the figure for the maximum allowable threshold ...

Page 188

... Host using the Maximum Tolerable Delay, and afterwards allowing CX28500 to take the remaining bus time to achieve 100% utilization. The second statistics set does not include spare time and indicates average utilization. ...

Page 189

... Max total in SLP Maximum amount of data in SLP internal buffers at any one time. 28500-DSH-002-C CX28500 PCI Bus Latency and Utilization Analysis Description Dependent on PCI bit mode and the value of PCI read latency. Dependent on PCI bit mode and the value of PCI read latency ...

Page 190

... Since Tables A-6 through A-8 are calculated for only one CX28500 device, total PCI system utilization for a two- device system is approximately double what is shown on the following pages. A.15 Differences in the Combined T1 Payload and Overhead Table Refer to ...

Page 191

... Throughout the calculation, each column relates only to that specific set of channels with one exception. The Utilization ABS Total represents the overall utilization of the CX28500. Table A-6. Example One ( MHz PCI Configuration Number of Ch Mem Available (KB) Packet Length (bits) Ext. Ch Rate (Kbps) PCI Freq ...

Page 192

... Mem Available (KB) Packet Length (bits) Ext. Ch Rate (Kbps) PCI Freq. (MHz) Read Latency Write Latency PCI Bit Mode 28500-DSH-002-C CX28500 PCI Bus Latency and Utilization Analysis 44-Byte Messages 168 x 1536K Channels 6 x 44.21M Channels 64-Bit PCI 32-Bit PCI 64-Bit PCI TOTAL ...

Page 193

... Max Total in SLP Buffer MAXDATA MAXDATA Max L (ms) ch Max L (ms) pci Max L (ms) ch 28500-DSH-002-C CX28500 PCI Bus Latency and Utilization Analysis 44-Byte Messages 168 x 1536K Channels 6 x 44.21M Channels 64-Bit PCI 32-Bit PCI 64-Bit PCI BUFFLEN 1592 1592 THR – RX 796 796 THR – ...

Page 194

... MHz PCI Configuration Max L (ms) pci Utilization Utilization Utilization Amnt Data Filled in Amnt Data Emptied in L pci 28500-DSH-002-C CX28500 PCI Bus Latency and Utilization Analysis 44-Byte Messages 168 x 1536K Channels 6 x 44.21M Channels 64-Bit PCI 32-Bit PCI 64-Bit PCI TX 0.091 0.124 RX 0.193 ...

Page 195

... Amnt Data Filled in L pci Amnt Data Emptied in L pci Spare Time (ms) Spare Time (ms) Spare Time (ms) Spare Time (cycles) 28500-DSH-002-C CX28500 PCI Bus Latency and Utilization Analysis 44-Byte Messages 168 x 1536K Channels 6 x 44.21M Channels 64-Bit PCI 32-Bit PCI 64-Bit PCI N 168 168 — ...

Page 196

... Utilization Utilization Utilization Utilization Amnt Data Filled in L pci Amnt Data Emptied in L pci 28500-DSH-002-C CX28500 PCI Bus Latency and Utilization Analysis 44-Byte Messages 168 x 1536K Channels 6 x 44.21M Channels 64-Bit PCI 32-Bit PCI 64-Bit PCI RX 599 2 TX 549 ...

Page 197

... CX28500’s PCI transactions while operating as a master and fast back-to-back feature enabled. CX28500 performs as a master while operating at 64-bit address-data, a burst write of 4 dwords, which are transferred during the first cycle and a burst write of 6 dwords which are transferred during the second cycle ...

Page 198

... CX28500’s PCI transactions while operating as a master, and fast back-to-back feature enabled. CX28500 performs as a master while operating at 32-bit address-data, a burst write of 2 dwords, which are transferred during the first cycle and a burst write of 3 dwords, which are transferred during the second cycle ...

Page 199

... Back Transactions Figure B-3 illustrates how CX28500 operates at 64-bit address-data and performs a burst read of 4 dwords followed by a burst read of 6 dwords. The fast back-to-back is disabled. It can be observed that the first cycle takes 5 PCLK cycles (with one PCLK post-data phase) and the second cycle of transferring 6 dwords requires 6 PCLK cycles ...

Page 200

... Back Transactions Figure B-4 illustrates how CX28500 operates at 32-bit address-data and performs a burst read of 2 dwords transfer during the first cycle and 3 dwords transfer during the second cycle. The fast back-to-back feature is disabled. It can be observed that the first cycle takes 5 PCLK cycles (with one PCLK post-data phase) and the second cycle of transferring 3 dwords requires 6 PCLK cycles ...