lc89962 Sanyo Semiconductor Corporation, lc89962 Datasheet
lc89962
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lc89962 Summary of contents
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... Ordering number : EN*5420 Overview The LC89962 and LC89962M are delay line circuits that provide a delayed signal period of NTSC format with an external low-pass filter. Features • Requires only the input of a 3.58-MHz clock to produce a 1H delayed signal and the external low-pass filter. ...
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... V1 [mVp-p] Output signal symbol V1 V2 Sine wave: 3.58 MHz, 200 mV p-p During this test, adjust Vbias so that the input signal DC level is 250 mV higher than the clamp level. LC89962, LC89962M Conditions = 5.0 V, CLK = 3.579545 MHz; 300 mV p-p DD Switch states SW1 SW2 SW3 ...
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... SW3 measure the delay time (TD), measure the delay time of the output signal to the input signal. In this measurement, the delay time associated with the low-pass filter must be excluded. LC89962, LC89962M ). O Input signal Sine wave: 200 kHz, 500 mV p-p No. 5420-3/6 ...
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... Pin Assignment Block Diagram LC89962, LC89962M No. 5420-4/6 ...
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... Test Circuit Sample Application Circuit LC89962, LC89962M No. 5420-5/6 ...
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... SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of September, 1996. Specifications and information herein are subject to change without notice. LC89962, LC89962M No. 5420-6/6 ...