M25P16-VME3 NUMONYX [Numonyx B.V], M25P16-VME3 Datasheet
M25P16-VME3
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M25P16-VME3 Summary of contents
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... BP2) ■ More than 20 year data retention ■ Packages – ECOPACK® (RoHS compliant) December 2007 VFQFPN8 (MP) 6 × (MLP8) VDFPN8 (ME (MLP8) SO8N (MN) 150 mils width SO8W (MW) 208 mils width SO16 (MF) 300 mils width Rev 13 M25P16 1/55 www.numonyx.com 1 ...
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... Active Power, Standby Power and Deep Power-down modes . . . . . . . . . 12 4.5 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.6 Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.7 Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.1 Write Enable (WREN 6.2 Write Disable (WRDI 6.3 Read Identification (RDID 6.4 Read Status Register (RDSR 6.4.1 6.4.2 6.4.3 2/55 WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 M25P16 ...
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... M25P16 6.4.4 6.5 Write Status Register (WRSR 6.6 Read Data Bytes (READ 6.7 Read Data Bytes at Higher Speed (FAST_READ 6.8 Page Program (PP 6.9 Sector Erase (SE 6.10 Bulk Erase (BE 6.11 Deep Power-down (DP 6.12 Release from Deep Power-down and Read Electronic Signature (RES Power-up and power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8 Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9 Maximum rating ...
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... Table 20. SO8 wide – 8 lead plastic small outline, 208 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 21. SO16 wide – 16-lead plastic small outline, 300 mils body width, mechanical data . . . . . . 51 Table 22. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Table 23. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4/55 threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 WI M25P16 ...
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... M25P16 List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. SO8, VFQFPN and VDFPN connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. SO16 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4. Bus master and memory devices on the SPI bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 5. SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 6. Hold condition activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 7. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 8. Write Enable (WREN) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 9 ...
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... Description 1 Description The M25P16 Mbit (2 Mbit × 8) serial Flash memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The memory is organized as 32 sectors, each containing 256 pages. Each page is 256 bytes wide ...
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... SO16 connections Don’t use 2. See Package mechanical M25P16 HOLD AI08517 section for package dimensions, and how to identify pin-1. M25P16 HOLD ...
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... To start the Hold condition, the device must be selected, with Chip Select (S) driven Low. 2.6 Write Protect (W) The main purpose of this input signal is to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP2, BP1 and BP0 bits of the Status Register). 8/55 M25P16 ...
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... M25P16 2.7 V supply voltage the supply voltage. CC 2.8 V ground the reference for the V SS supply voltage. CC Signal description 9/55 ...
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... Serial Data output (Q) line at a time, the other devices are high impedance. Resistors R (represented in that the M25P16 is not selected if the Bus Master leaves the S line in the high impedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance ...
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... M25P16 Example pF, that is R*C p Master never leaves the SPI bus in the high impedance state for a time period shorter than 5 µs. Figure 5. SPI modes supported CPOL CPHA µs <=> the application must ensure that the Bus p MSB ...
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... While in the Deep Power-down mode, the device ignores all Write, Program and Erase instructions (see mechanism, when the device is not in active use, to protect the device from inadvertent Write, Program or Erase instructions. 12/55 ). Deep Power-down (DP)). This can be used as an extra software protection ). PP Page Program , The CC2 M25P16 (PP)). ). The BE . CC1 ...
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... Protection modes The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the presence of excessive noise. To help combat this, the M25P16 features the following data protection mechanisms: ● Power on reset and an internal timer (t changes while the power supply is outside the operating specification ● ...
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... Upper quarter (8 sectors 31) Upper half (16 sectors 31) All sectors (32 sectors 31) All sectors (32 sectors 31) Figure 6). Unprotected area (1) All sectors (32 sectors 31) Lower 31/32nds (31 sectors 30) Lower seven-eighths (28 sectors 27) Lower three-quarters (24 sectors 23) Lower half (16 sectors 15) none none Figure 6). M25P16 ...
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... M25P16 Figure 6. Hold condition activation C HOLD Hold condition (standard use) Operating features Hold condition (non-standard use) AI02029D 15/55 ...
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... Figure 7. Block diagram HOLD 16/55 High voltage Control Logic I/O Shift Register Address Register and Counter 00000h 256 bytes (page size) Generator Status 256 byte Register Data Buffer 1FFFFFh 000FFh X Decoder M25P16 Size of the read-only memory area AI04987 ...
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... M25P16 Table 3. Memory organization Sector Address range 1F0000h 1E0000h 1D0000h 1C0000h 1B0000h 1A0000h 190000h 180000h 170000h 160000h 150000h 140000h 130000h 120000h 110000h 100000h 0F0000h 0E0000h ...
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... All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues unaffected. Note: Output Hi-Z is defined as the point where data out is no longer driven. 18/55 Table 4. M25P16 ...
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... M25P16 Table 4. Instruction set Instruction WREN Write Enable WRDI Write Disable RDID Read Identification RDSR Read Status Register WRSR Write Status Register READ Read Data Bytes Read Data Bytes at Higher FAST_READ Speed PP Page Program SE Sector Erase BE Bulk Erase DP Deep Power-down Release from Deep ...
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... Write Status Register (WRSR) instruction completion ● Page Program (PP) instruction completion ● Sector Erase (SE) instruction completion ● Bulk Erase (BE) instruction completion Figure 9. Write Disable (WRDI) instruction sequence 20/55 (Figure 9) resets the Write Enable Latch (WEL) bit Instruction D High Impedance AI03750D M25P16 ...
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... M25P16 6.3 Read Identification (RDID) The Read Identification (RDID) instruction allows to read the device identification data: ● Manufacturer identification (1 byte) ● Device identification (2 bytes) ● A Unique ID code (UID) (17 bytes, of which 16 available upon customer request). The manufacturer identification is assigned by JEDEC, and has the value 20h for Numonyx. ...
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... BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. The Bulk Erase (BE) instruction is executed if, and only if, all Block Protect (BP2, BP1, BP0) bits are 0. 22/ BP2 Figure 11. BP1 BP0 WEL Block Protect bits Write Enable Latch bit Write In Progress bit Table 2) becomes M25P16 b0 WIP ...
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... M25P16 6.4.4 SRWD bit The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W) signal allow the device to be put in the Hardware Protected mode (when the Status Register Write Disable (SRWD) bit is set to ‘ ...
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... Figure 12. Write Status Register (WRSR) instruction sequence 24/55 Figure 12. Table 2. The Write Status Register (WRSR) instruction also allows Instruction High Impedance MSB M25P16 ) is W Status Register AI02282D ...
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... M25P16 Table 7. Protection modes W SRWD signal bit 1 0 Software 0 0 Protected 1 1 Hardware Protected defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in Table 6. The protection features of the device are summarized in When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial ...
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... High Impedance Q 1. Address bits A23 to A21 are Don’t care. 26/55 Figure 13 Instruction 24-bit address MSB Data Out MSB M25P16 Data Out 2 7 AI03748D ...
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... M25P16 6.7 Read Data Bytes at Higher Speed (FAST_READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the Read Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23- A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C). ...
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... Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A Page Program (PP) instruction applied to a page which is protected by the Block Protect (BP2, BP1, BP0) bits (see 28/55 Figure 15. Table 2 and Table 3) is not executed. M25P16 ...
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... M25P16 Figure 15. Page Program (PP) instruction sequence Data byte MSB 1. Address bits A23 to A21 are Don’t care Instruction 24-bit address MSB Data byte 3 ...
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... Address bits A23 to A21 are Don’t care. 30/ valid address for the Sector Erase (SE) instruction. Chip Select (S) Figure 16. Table 2 and Table 3) is not executed Instruction MSB Bit Address AI03751D M25P16 ) is SE ...
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... M25P16 6.10 Bulk Erase (BE) The Bulk Erase (BE) instruction sets all bits to ‘1’ (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). ...
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... Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Figure 18. Deep Power-down (DP) instruction sequence 32/55 14). Figure 18 Instruction CC1 before the supply current is reduced Standby mode Deep Power-down mode M25P16 CC2 AI03753D ...
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... Deep Power-down mode. The instruction can also be used to read, on Serial Data output (Q), the old-style 8-bit electronic signature, whose value for the M25P16 is 14h. Please note that this is not the same as, or even a subset of, the JEDEC 16-bit electronic signature that is read by the Read Identifier (RDID) instruction ...
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... C Instruction D High Impedance Q 1. The value of the 8-bit electronic signature, for the M25P16, is 14h. Figure 20. Release from Deep Power-down (RES) instruction sequence Instruction D High Impedance Q Driving Chip Select (S) High after the 8-bit instruction byte has been received by the device, but before the whole of the 8-bit electronic signature has been transmitted for the first time (as shown in still ensures that the device is put into Standby Power mode ...
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... M25P16 7 Power-up and power-down At power-up and power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied on V ● V (min) at power-up, and then for a further delay ● power-down SS A safe configuration is provided in To avoid data corruption and inadvertent write operations during power-up, a Power On Reset (POR) circuit is included ...
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... FFh). The Status Register contains 00h (all Status Register bits are 0). 36/55 Program, Erase and Write commands are rejected by the device Chip selection not allowed tVSL tPUW threshold WI Parameter M25P16 Read access allowed Device fully accessible time AI04009C Min Max Unit ...
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... M25P16 9 Maximum rating Stressing the device above the rating listed in cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability ...
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... Min Max Unit 100 000 Cycles per sector 10 000 20 years Min Max 30 5 0. 0. Input and output timing reference levels 0.7V CC 0.5V CC 0.3V CC AI07455 Min Max = M25P16 Unit V °C °C Unit Unit pF pF ...
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... M25P16 Table 14. DC characteristics Symbol I Input leakage current LI I Output leakage current LO I Standby current CC1 Deep Power-down I CC2 current I Operating current (READ) CC3 I Operating current (PP) CC4 I Operating current (WRSR) CC5 I Operating current (SE) CC6 I Operating current (BE) CC7 V Input low voltage IL V Input high voltage ...
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... S High to Standby mode without Read (4) t RES1 Electronic Signature S High to Standby mode with Read Electronic (4) t RES2 Signature t Write Status Register cycle time W 40/55 T9HX technology Test conditions specified in Table 10 Parameter (5) (peak to peak) (5) (peak to peak) M25P16 ) (1) and Table 12 (2) Min Typ Max Unit D.C. 75 MHz D.C. 33 MHz 6 6 0.1 V/ns 0.1 V/ns ...
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... M25P16 Table 15. AC characteristics (grade 6, Applies only to products made with T9HX technology, identified with process digit ‘4’ Symbol Alt. Page Program cycle time (256 bytes) Page Program cycle time (n bytes, where ( Page Program cycle time (n bytes, where ...
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... Table 12 Min Typ Max D. 0.1 0 100 100 3 3 1.8 1.5 15 0.8 5 (7) int(n/8) × 0.025 M25P16 Unit MHz MHz ns ns V/ns V/ µs µs µ ...
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... M25P16 Table 16. AC characteristics (25 MHz operation, grade 3) Test conditions specified in Symbol Alt. (6) t Sector Erase cycle time SE (6) t Bulk Erase cycle time BE 1. Preliminary data must be greater than or equal Value guaranteed by characterization, not 100% tested in production. 4. Expressed as a slew-rate. ...
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... DC and AC parameters Figure 24. Write Protect setup and hold timing during WRSR when SRWD = 1 W tWHSL High Impedance Q Figure 25. Hold timing HOLD 44/55 tHLCH tCHHL tCHHH tHLQZ tHHQX M25P16 tSHWL AI07439 tHHCH AI02032 ...
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... M25P16 Figure 26. Output timing S C tCLQV tCLQX tCLQX Q ADDR.LSB IN D tCH tCLQV tCL tQLQH tQHQL DC and AC parameters tSHQZ LSB OUT AI01449e 45/55 ...
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... Figure 27. VFQFPN8 (MLP8) 8-lead very thin fine pitch quad flat package no lead, 6 × 5 mm, package outline Drawing is not to scale. 2. The circle in the top view of the package indicates the position of pin 1. 46/ 0. θ 0. aaa ddd C M25P16 70-ME ...
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... M25P16 Table 17. VFQFPN8 (MLP8) 8-lead very thin fine pitch quad flat package no lead, 6 × 5 mm, package mechanical data Symbol Θ aaa bbb ddd millimeters Typ Min Max 0.85 0.80 1.00 0.00 0.05 0.65 0.20 0.40 0.35 0.48 6.00 5.75 3.40 3.20 3.60 5.00 4.75 4.00 3.80 4.30 1.27 – – 0.10 0.00 0.60 0.50 0.75 12° 0.15 0.10 0.05 Package mechanical inches Typ ...
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... D2 Max should not exceed (D – K – 2 × L). 48/ millimeters Typ Min Max 0.85 1.00 0.00 0.05 0.40 0.35 0.48 8.00 (1) 5.16 0.05 6.00 4.80 1.27 – – 0.82 0.50 0.45 0.60 0. ddd VDFPN-02 inches Typ Min 0.033 0.000 0.016 0.014 0.315 0.203 0.236 0.189 0.050 – 0.032 0.020 0.018 8 M25P16 Max 0.039 0.002 0.019 0.002 – 0.024 0.006 ...
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... M25P16 Figure 29. SO8N – 8 lead plastic small outline, 150 mils body width, package outline A2 1. Drawing is not to scale. Table 19. SO8N – 8 lead plastic small outline, 150 mils body width, package mechanical data Symbol ccc ccc ...
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... Typ Min Max 2.50 0.00 0.25 1.51 2.00 0.40 0.35 0.51 0.20 0.10 0.35 0.10 6.05 5.02 6.22 7.62 8.89 1.27 – – 0° 10° 0.50 0. inches Typ Min 0.000 0.059 0.016 0.014 0.008 0.004 0.198 0.300 0.050 – 0° 0.020 8 M25P16 6L_ME Max 0.098 0.010 0.079 0.020 0.014 0.004 0.238 0.245 0.350 – 10° 0.031 ...
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... M25P16 Figure 31. SO16 wide – 16-lead plastic small outline, 300 mils body width, package outline SO-H 1. Drawing is not to scale. Table 21. SO16 wide – 16-lead plastic small outline, 300 mils body width, mechanical data Symbol θ ddd D 16 ...
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... Grade 3 is available only in devices delivered in SO8N packages. Note: For a list of available options (speed, package, etc.), for further information on any aspect of this device or when ordering parts operating at 75 MHz (0.11 µm, process digit ‘4’), please contact your nearest Numonyx Sales Office. 52/55 M25P16 (1) M25P16 – ...
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... M25P16 13 Revision history Table 23. Document revision history Date Revision 16-Jan-2002 23-Apr-2002 13-Dec-2002 15-May-2003 20-Jun-2003 24-Sep-2003 24-Nov-2003 17-May-2004 01-Apr-2005 01-Aug-2005 20-Oct-2005 27-Feb-2006 04-Jul-2006 0.1 Target Specification Document written Clarification of descriptions of entering Standby Power mode from Deep Power-down mode, and of terminating an instruction sequence or data- ...
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... Section 7: Power-up and power- ratings. Grade 3 and Table 16: AC characteristics added. Section 6.3: Read Identification Table 5: Read Identification Table 4: Instruction in Table 14: DC CC3 in Table 15: AC characteristics (grade C updated. ratings. in Table 15: AC characteristics (grade CLQV M25P16 Note 1 added Figure 4: Section 11: (RDID). set. ...
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... M25P16 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT ...