IDT70V24 IDT [Integrated Device Technology], IDT70V24 Datasheet - Page 11

• Manufacturer Part Number: IDT70V24
• Description: HIGH-SPEED 3.3V 4K x 16 DUAL-PORT STATIC RAM
• Manufacturer: IDT [Integrated Device Technology]

NOTES:
1. R/W or CE or UB & LB must be high during all address transitions.
2. A write occurs during the overlap (t
3. t
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state.
6. Timing depends on which enable signal is asserted last, CE, R/W or byte control.
7. This parameter is guaranteed by device characterization, but is not production tested.Transition is measured 0mV from low or high-impedance voltage with Output
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of t
9. To access SRAM, CE = V
CE
CE
CE
ADDRESS
ADDRESS
IDT70V24S/L
High-Speed 4K x 16 Dual-Port Static RAM
DATA
Test Load (Figure 2).
bus for the required t
the entire t
UB
WR
DATA
DATA
or
or
or
is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
or
SEM
SEM
SEM
R/
R/
OUT
OE
LB
W
W
IN
IN
EW
(9)
(9)
(9)
(9)
time.
DW
. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t
IL
, UB or LB = V
t
AS
EW
t
AS
(6)
or t
(6)
WP
) of a low UB or LB and a LOW CE and a LOW R/W for memory array writing cycle.
(4)
IL
, SEM = V
IH
t
WZ
. To access semaphore, CE = V
(7)
t
t
AW
AW
t
WC
t
WC
t
WP
t
EW
(2)
(2)
6.42
11
WP
t
CE UB LB
t
DW
DW
IH
or (t
W
or UB and LB = V
WZ
+ t
DW
Industrial and Commercial Temperature Ranges
t
WR
) to allow the I/O drivers to turn off and data to be placed on the
(3)
t
t
DH
t
WR
DH
IH
t
OW
and SEM = V
(3)
IL
t
HZ
. Either condition must be valid for
(7)
(4)
2911 drw 08
2911 drw 09
WP
.