TSS901EMA-E ATMEL [ATMEL Corporation], TSS901EMA-E Datasheet
TSS901EMA-E
Related parts for TSS901EMA-E
TSS901EMA-E Summary of contents
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Features • 3 identical bidirectional link channels allowing full duplex communication under selectable transmit rate from 1. 200 Mbit/s in each direction • A COmmunication Memory Interface (COMI) provides autonomous accesses to a communication memory which are controlled ...
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Introduction The TSS901E provides an interface between a Data-Strobe link according to the IEEE Std 1355-1995 specification carrying the simple interprocessor communication protocol data processing node consisting of a CPU and communication and data memory. The TSS901E provides HW supported ...
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DS-link macro cell (DSM), receive and transmit sections (each including FIFOs) and a protocol processing unit (PPU). Each channel allows full duplex communication up to 200 Mbit/s in each direction. With protocol command ...
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Transparent Mode (default after reset): This mode allows complete transparent data transfer between two nodes without performing any interpretation of the databytes and without generating any acknowledges completely up to the host CPU to interpret the received ...
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TSS901E Control A feature of the TSS901E is the possibility to control the TSS901E not only via HOCI but via one of the three links. This allows to use the TSS901E in systems without a local controller (µCon- by Link ...
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Fault Tolerance The IEEE Std 1355-1995 specifies low level checks as link disconnect detection and parity check at token level. The TSS901E provides, through the Protocol Processing Unit, features to reset a link or all links inside the TSS901E, to ...
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Register Set This chapter describes the TSS901E registers which can be read or written by the HOCI or via the link (in case the "control by link" is enabled) to control TSS901E operations. All TSS901E control operations are performed by ...
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Register Address Map The addresses of the TSS901E registers are directly mapped with pins HADR7 - 0. The tables below shows the addresses of all the TSS901E registers depending on the HOCI port width. TSS901E status and control registers Port ...
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Port Width / Address (hex ...
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Port Width / Address (hex ...
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Port Width / Address (hex ...
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TSS901E GPIO These registers are only enabled when the TSS901E is configured for "control by link" using the Control Registers 'BOOTLINK' pin. Port Width / Address (hex TSS901E 12 ...
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Signal Description The Figure below shows the TSS901E (also called SMCS332) embedded in a typical module environment: This section describes the pins of the TSS901E. Groups of pins represent busses where the highest number is the MSB Output; ...
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Signal Name HOSTBIGE BOOTLINK CMCS(1:0)* CMRD* CMWR* CMADR(15:0) CMDATA(31:0) COCI COCO CAM CPUR* SES(3:0)* LDI1 LSI1 LDO1 LSO1 LEN1 LDI2 LSI2 LDO2 LSO2 LEN2 LDI3 LSI3 LDO3 LSO3 LEN3 TRST* TSS901E 14 Type Function 1: host I/F Big Endian I ...
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Signal Name TCK TMS TDI TDO RESET* CLK CLK10 PLLOUT VCC GND 4167F–AERO–06/07 Type Function Test Clock. Provides an asynchronous clock for JTAG I boundary scan. I Test Mode Select. Used to control the test state machine. Test Data Input. ...
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Electrical Characteristics The following data is provided for information only; for the guaranteed values, refer to Atmel pro- curement specification. Absolute Maximum Ratings Supply Voltage I/O Voltage Operating Temperature Range (Ambient) Junction Temperature Storage Temperature Range Stresses above those listed ...
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PLL Filter The pin PLLOUT should be connected as shown below 249Ω ± 5%, ¼1/ 1nF, ± 5%, 20V C2 = 15nF, ± 5%, 20V 4167F–AERO–06/07 TSS90E PLLOUT TSS901E 17 ...
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Timing Parameters Clock Signals 1) CLK period CLK width high CLK width low Note: 1) CLK10 period CLK10 width high CLK10 width low Note: TSS901E 18 Description 1) Max. 25 MHz Description 1) Typically 10 MHz Symbol Min. Max. t ...
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Reset RESET setup before CLK high RESET low pulse width Output disable after CLK high Output enable after CLK high CAM, HOSTBIGE, BOOTLINK setup before RESET high 4167F–AERO–06/07 Description TSS901E Symbol Min. Max RSTS ...
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Host Read HSEL*, HRD* and TSS901EADR and HADR setup before CLK high HADR, TSS901EADR hold after HSEL*, HRD* high HRD* pulse width high HACK low after HRD*, HSEL* active and TSS901EADR valid HACK high after CLK high HACK disable after ...
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Host Write HSEL*, HWR* and TSS901EADR and HADR setup before CLK high HADR, TSS901EADR hold after HSEL*, HWR* high HWR* pulse width high HACK low after HWR*, HSEL* active and TSS901EADR valid HACK high after HSEL* and HWR* and TSS901EADR ...
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COMI Read CMCS0*, CMCS1* and CMRD* low and CMADR valid after CLK high CMCS0*, CMCS1* or CMRD* high after CLK high CMCS0*, CMCS1*, CMRD*, CMADR pulse width CMDATA setup before CMCS0* or CMCS1* or CMRD* high or new address on ...
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COMI Write CMCS0*, CMCS1* and CMWR* low and CMADR valid after CLK high CMCS0*, CMCS1* or CMWR* high after CLK high CMCS0*, CMCS1*, CMWR* pulse width CMDATA valid after CLK high CMDATA valid before CMCS0* or CMCS1* or CMWR* high ...
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COMI Arbitration COM Interface disable after CLK low COM Interface enable after CLK high COCI setup before CLK low COCO low after CLK low COCO high after CLK high 3) COCO pulse width Note: TSS901E 24 Description ...
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CPUR, SES, Interrupt CPUR*, SESx*, HINTR* delay after CLK high Links Bit Period LDOx, LSOx output skew Data/Strobe edge separation 4167F–AERO–06/07 CLK t OUTC CPUR SESx HINTR Description LSOx LDOx t LOUT LDIx t LDSI LSIx Description TSS901E Symbol Min. ...
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Test Port (JTAG) TCK period TCK width high TCK width low TMS, TDI setup before TCK high TMS, TDI hold after TCK high TDO delay after TCK low TRST* pulse width TSS901E Inputs setup before TCK high TSS901E Inputs hold ...
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Package Drawings MQFPL 196 4167F–AERO–06/07 Code: FX Date:13/10/00 TSS901E 27 ...
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Pin Assignment Pin Number 1 VCC 2 GND 3 GND 4 CLK 5 RESET* 6 CLK10 7 HOSTBIGE 8 TCK 9 TMS 10 TDI 11 TRST* 12 TDO 13 VCC 14 GND 15 HSEL* 16 HRD* 17 HWR* 18 HACK ...
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Pin Number 45 HDATA2 46 HDATA3 47 HDATA4 48 HDATA5 49 HDATA6 50 VCC 51 GND 52 HDATA7 53 HDATA8 54 HDATA9 55 HDATA10 56 HDATA11 57 VCC 58 GND 59 HDATA12 60 HDATA13 61 HDATA14 62 HDATA15 63 HDATA16 ...
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... Ordering Information Part-number TSS901EMA-E 5962-01A1701QXC 5962-01A1701VXC Document Revision History Changes from 1. Changed web address of location of TSS901E User’s Manual. Page 1. 4167D to 4167E Changes from to 1. Updated Ordering Information. 4167E to 4167F TSS901E 30 Temp. Range Package 25° C MQFPL196 -55° C +125° C MQFPL196 -55° C +125° C ...
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Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 ...