IDT72V36100 IDT [Integrated Device Technology], IDT72V36100 Datasheet - Page 12

• Manufacturer Part Number: IDT72V36100
• Manufacturer: IDT [Integrated Device Technology]

NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
IDT72V3640/50/60/70/80/90/110 3.3V HIGH DENSITY SUPERSYNC II
1,024 x 36, 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36
LD
0
0
0
X
1
1
1
WEN
1
1
0
X
1
0
1
Figure 3. Programmable Flag Offset Programming Sequence
REN
0
1
1
1
X
0
1
SEN
1
1
0
1
X
X
X
WCLK
X
X
X
X
TM
36-BIT FIFO
12
RCLK
X
X
X
X
X
Serial shift into registers:
1 bit for each rising WCLK edge
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
Parallel write to registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
20 bits for the 72V3640
22 bits for the 72V3650
24 bits for the 72V3660
26 bits for the 72V3670
28 bits for the 72V3680
30 bits for the 72V3690
32 bits for the 72V36100
34 bits for the 72V36110
Read Memory
No Operation
Write Memory
No Operation
IDT72V3640
IDT72V3650
IDT72V3660
IDT72V3670
IDT72V3680
IDT72V3690
IDT72V36100
IDT72V36110
COMMERCIAL AND INDUSTRIAL
4667 drw 06
TEMPERATURE RANGES