SDA9489X ETC [List of Unclassifed Manufacturers], SDA9489X Datasheet

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Edition Feb. 28, 2001 6251-562-1PD PRELIMINARY DATA SHEET SDA 9489X PIP IV Advanced SDA 9589X SOPHISTICUS High-End Picture-In-Picture ICs ...

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SDA 9489X SDA 9589X High-end Picture-In-Picture (PIP) ICs Version 1.3 General Description SDA 9489X ’PIP IV Advanced’ and SDA 9589X ’SOPHISTICUS’ belong to a new generation of Picture- in-Picture (PiP) processors that combine high-quality digital PIP signal processing, digital multistandard ...

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SDA 9489X SDA 9589X 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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SDA 9489X SDA 9589X 4.11 Data Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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SDA 9489X SDA 9589X 1 Features • Single chip solution: – AD-conversion for CVBS or Y/C or YUV synchronization of inset channel, decimation filtering, embedded memory, RGB- matrix, DA-conversion, RGB/YUV switch, data-slicer and clock generation integrated on chip • Analog ...

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SDA 9489X SDA 9589X – Freeze picture – Coarse positioning at 4 corners of the parent picture – Fine positioning at steps of 4 pixels and 2 lines – Wipe in / out programmable with 3 time periods • Output ...

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SDA 9489X SDA 9589X 2 Pin Configuration XIN XQ HSP VSP SDA SCL VDD VSS I2C INT IN1 IN2 IN3 FSW Figure 2-1 Pinning Figure 2-2 Package Outlines Micronas CVBS1 1 28 VREFM 2 27 CVBS2 3 26 VREFL 4 ...

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SDA 9489X SDA 9589X Numb Name Type er 1 XIN HSP I/TTL 4 VSP I/TTL 5 SDA I/O 6 SCL I 7 VDD S 8 VSS S 9 I2C I 10 INT O/TTL 11 IN1 ...

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SDA 9489X SDA 9589X 3 Block Diagram DEMUX MUX Figure 3-1 Block Diagram Micronas DUV/DCHR DCVBS/DY Preliminary Data Sheet Block Diagram 3-9 ...

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SDA 9489X SDA 9589X 4 System Description 4.1 Analog Frontend 4.1.1 Input Selection An analog inset CVBS signal can be fed to the inputs CVBS1-3 of SDA 9589X/SDA 9489X. Each of these sources is selectable via I can be used ...

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SDA 9489X SDA 9589X The clamping pulse can be shifted in position (CLMPIST) and length (CLMPID) to adjust to the specific application. The ADCs are driven by a 20.25 MHz free running crystal clock which is not related to the ...

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SDA 9489X SDA 9589X 255 upper headroom 217 white black 68 4 lower headroom 0 Figure 4-3 CVBS/Y and chroma ADC input signal range 255 240 upper headroom 212 75% U 128 44 16 lower headroom 0 Figure 4-4 UV ...

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SDA 9489X SDA 9589X 4.2 Inset Synchronization Horizontal and vertical sync pulses are separated after elimination of the high frequency components of the CVBS signal by a low pass filter. Horizontal sync pulses are generated by a digital phase-locked-loop (DPLL). ...

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SDA 9489X SDA 9589X by a digital PLL. At SECAM operation the PLL runs free and generates the line-wise alternating subcarriers. A CORDIC structure demodulates the frequency-modulated UV signals. The following SECAM de-emphasis filter characteristic is adjustable (DEEMP). The chroma ...

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SDA 9489X SDA 9589X CKILL COLON Table 4-4 Color-killer adjustment The bandwidth of the chroma filter is adjustable via CHRBW. The bandwidth depends on whether the decoder is ...

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SDA 9489X SDA 9589X Received signal BLACK value BLANK value LMOFST ='00' (no additional offset) BLACK value BLANK value LMOFST ='00' (no additional offset) Figure 4-6 Black level correction of luminance signal The color carrier is removed out of a ...

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SDA 9489X SDA 9589X SIZEHOR horizontal scaling 6:1 Table 4-5 Number of stored pixel per line dependent on SIZEHOR SIZEVER vertical scaling 2:1 ...

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SDA 9489X SDA 9589X picture size. Then the size changes immediately. Equal to the wipe process, the zooming direction depends on the coarse position (CPOS). 625 lines 132 1 0 2,03 130 2 0 2,06 128 3 ...

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SDA 9489X SDA 9589X 0 0 2,00 324 1 0 2,02 320 2 0 2,05 316 3 0 2,08 312 4 0 2,10 308 5 0 2,13 304 6 0 2,16 300 7 0 2,19 296 8 0 2,22 292 ...

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SDA 9489X SDA 9589X 4.6.4 Multi Display Mode SDA 9589X and SDA 9489X offer the feature to display a sub-picture more than once. The picture size and arrangement depends on the display mode (DISPMOD) and not on SIZEHOR or SIZEVER. ...

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SDA 9489X SDA 9589X The D1.5 mode is suited for displaying split screen on 16:9 tubes keeping the aspect ratio. The DW1 format covers the full height of the screen. 4.6.6 Multi-PiP Mode There is a great variety of multi-pip ...

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SDA 9489X SDA 9589X Display DISPMOD Mode ...

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SDA 9489X SDA 9589X automatically, if the described restrictions are not fulfilled. Then only every second incoming field is shown (field mode). Field mode normally shows joint-lines. This is caused by an update of the memory during read out. The ...

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SDA 9489X SDA 9589X HSP VSP VSPDEL VSPD field 0 window (internal) tH (16) ←s values in brackets () apply for 100Hz systems Figure 4-8 Field detection and phase adjustment of vertical pulse (VSP) Depending on the phase ...

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SDA 9489X SDA 9589X Inset Parent 1) Frequency Frequency (HSP/VSP) 50 50i 50 60i 60 50i 60 60i 50 50p 50 60p 60 50p 60 60p 50 100i 50 120i 60 100i 60 120i 50 (S)VGA 60 (S)VGA 1) standard ...

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SDA 9489X SDA 9589X 4.7.2 Mixed Standard Applications And (S)VGA Support remark (kHz) apel aline V 720X576@50Hz 15.6 (TV) 702X488@60Hz 15.7 (TV) 720X576@100Hz 31.2 (TV 100 Hz) 702X488@120Hz 31.2 (TV 120 Hz) ...

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SDA 9489X SDA 9589X SDA 9589X and SDA 9489X allow multiple scan rates for the use in desktop video applications, VGA compatible or 100Hz TV sets. All features are provided in ’normal’ operating modes at auto detected 50Hz and 60 ...

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SDA 9489X SDA 9589X DISPSTD DISPMOD > Table 4-16 Display standard selection If a 625 lines picture is shown with a 525 lines parent ...

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SDA 9489X SDA 9589X CPOS Coarse Position upper left 0 1 upper right 1 0 lower left 1 1 lower right Table 4-17 Coarse Positioning There are 256 horizontal locations (4 pixel increments) and 256 vertical ...

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SDA 9489X SDA 9589X CPOS='01' CPOS='00' CPOS='10' CPOS='11' Figure 4-11 Wipe display If WIPESPD is set accordingly, PIPON controls the wipe operation. When PIPON changes the wipe operation starts. During this period, the readable PIPSTAT indicates the ongoing wipe-process. A ...

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SDA 9489X SDA 9589X 0.1 Figure 4-12 Characteristics of selectable peaking factors (0.5 = band limit) Coring should be switched on by YCOR to reduce noise, which is ...

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SDA 9489X SDA 9589X 4.8.3 Frame Generation And Colored Background With FRSEL a colored frame is added to the inset picture. The chip can display two different types of frames, one simple monochrome frame and a more sophisticated frame giving ...

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SDA 9489X SDA 9589X 4096 frame colors are programmable by FRY, FRU, and FRV, 4 bits for each component. Horizontal and vertical width of the frame are programmable independently by FRWIDH and FRWIDV. If desired, frame color is displayed over ...

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SDA 9489X SDA 9589X display inset format picture format 4:3 4:3 4:3 4:3 16:9 4:3 16:9 16:9 Table 4-20 Format conversion using HZOOM For variations of parental horizontal frequency (e.g. VCR), a digital correction of the position is useful to ...

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SDA 9489X SDA 9589X 4.9 On Screen Display (OSD) 4.9.1 Display Format The on screen display allows to insert a block of 5 characters into each of the PIP pictures. The characters are placed in a box (background) whose width ...

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SDA 9489X SDA 9589X 4.9.3 Character and Character Background Color The character’s color is either same as frame color (CHRFRC) or the character appears with a grey value programmable with CHRY. The character’s background box is influenced by CHRBGON and ...

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SDA 9489X SDA 9589X the clamping and blanking pulse because of the modified clock frequency, but the pulse length is kept nearly constant. Parent Video HSP allowed HSP range BLANKP a c CLAMPP Figure 4-20 PIP horizontal blanking timing READD ...

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SDA 9489X SDA 9589X enhanced resolution of 0.5 LSB. The maximum possible offset amounts to 7.5 LSBs. In YUV mode (OUTFOR = ’1’) the action depends on the setting of BLKINVR and BLKINVB. If BLKINVR (BLKINVB) is active the offset ...

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SDA 9489X SDA 9589X 4.11 Data Slicer Depending on SERVICE, Closed Caption data (’Line 21’) or WSS (Widescreen signalling) is sliced by the digital data slicer and can be read out from I line number of the sliced data is ...

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SDA 9489X SDA 9589X registers DATAA/DATAB are read. Both modes are useful to avoid continous polling of the I2C bus. The micro-controller initiates I2C transfers only when required. while (1){ i2c_read pip4_adr, status_reg_adr, status if (status & data_valid_mask) { i2c_read_inc ...

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SDA 9489X SDA 9589X 5 Application Examples The following two figures show 100/120Hz applications with the Micronas Featurebox SDA 9400/01. As the chip supports two I2C addresses and owns a RGB switch dual-PiP applications are easy to implement. The arrangement ...

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SDA 9489X SDA 9589X smaller than 1/9. The output of an OSD/Text processor may be fed to the RGB switch of the SDA 9589X/SDA 9489X. Micronas Preliminary Data Sheet Application Examples 5-42 ...

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SDA 9489X SDA 9589X Bus 2 6 Bus Address Write Address1 1 Read Address1 1 Table 6-1 Primary Address (pin 9=’low-level’) Write Address2 1 Read Address2 1 Table 6-2 Secondary Address (pin 9 = ...

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SDA 9489X SDA 9589X 2 6 bus Command Table Subadd (Hex 00h PIPON CPOS1 01h POSHOR7 POSHOR6 POSHOR5 POSHOR4 POSHOR3 POSHOR2 POSHOR1 POSHOR0 02h POSVER7 POSVER6 POSVER5 POSVER4 POSVER3 POSVER2 POSVER1 POSVER0 03h VFP3 VFP2 04h ...

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SDA 9489X SDA 9589X Subadd (Hex 17h MAT1 MAT0 18h OUTFOR UVPOLAR 19h (reserved) BGFRC 1Ah SATADJ3† SATADJ2 1Bh XDSCLS4 XDSCLS3 1Ch UVSEQ MPIPBG 1Dh (reserved) (reserved) 1Eh POSOFV2 POSOFV1 POSOFV0 POSOFH4 POSOFH3 POSOFH2 POSOFH1 POSOFH0 1Fh (reserved) ...

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SDA 9489X SDA 9589X 2 6 Bus Command Description Subaddress 00h PIPON D7 switches the PIP insertion on 0 PIP insertion off 1 PIP insertion on CPOS D6 D5 coarse positioning of the picture 0 0 upper left ...

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SDA 9489X SDA 9589X PROGEN D2 for compatibility with progressive scan systems 0 each line of PIP is read once (normal operation) 1 each line of PIP is read twice (line doubling operation) FIESEL D1 D0 set field or frame ...

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SDA 9489X SDA 9589X Subaddress 03h HFP changes the position of the horizontal acquisition window by steps of 2 pixel -16 pixel (-0.8 ←s), most right position the image .. 0 ...

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SDA 9489X SDA 9589X FREEZE D5 interrupts the inset picture writing and displays still picture 0 live picture 1 still picture MOSAIC D4 hides picture details, intended for use with parental control 0 mosaic mode off 1 mosaic mode on ...

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SDA 9489X SDA 9589X Subaddress 05h FPSTD D7 D6 forces the parent standard to one of the following modes 0 0 auto-detect parent standard 0 1 50Hz/625 lines parent standard forced 1 0 60Hz/525 lines parent standard forced 1 1 ...

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SDA 9489X SDA 9589X Subaddress 06h HSPINV D7 inverts the polarity of HSP 0 no inversion, raising edge is sync reference 1 HSP inverted, falling edge is sync reference VSPINV D6 inverts the polarity of VSP 0 no inversion, raising ...

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SDA 9489X SDA 9589X INFRM D6 actives inner frame (4 pixel width, 2 lines height) for multi-PIP display 0 inner frame off 1 inner frame on VPSRED D5 reduces vertical picture size to suppress black bars in 16:9 programs 0 ...

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SDA 9489X SDA 9589X VERBLK D5 switches the vertical blanking mode 0 blanking level at DAC outputs only during line-blanking intervals 1 blanking level at DAC outputs during line-blanking intervals and field- blanking intervals, 16 lines following the parent vertical ...

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SDA 9489X SDA 9589X DISPMOD D6 D5 selects display modes with equal pictures 0 0 single PiP mode x1/9 PiP (same content x1/16 PiP (same content (reserved) CLPDEL ...

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SDA 9489X SDA 9589X AGCVAL AGC value for fixed mode (AGCMD=’11’ input voltage 0.5 Vpp .. input voltage 1 Vpp .. input voltage 1.5 ...

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SDA 9489X SDA 9589X CLMPIST D3 D2 adjusts delay of clamping pulse for ADC refered to the horizontal sync 0 0 1.0← 1.5← 2.0← 2.5←s LMOFST D1 D0 modifies black to blank level offset ...

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SDA 9489X SDA 9589X YCDEL adjusts the delay between luminance and chrominance -8 pixel (-0.4 ←s with respect to undecimated picture pixel .. +7 pixel (0.35 ...

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SDA 9489X SDA 9589X CKILL D1 D0 damping of color carrier to switch color off color always off Subaddress 0Eh BGPOS D7 adjusts position of burst ...

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SDA 9489X SDA 9589X ACCFIX D2 disables the automatic chroma control (ACC) 0 ACC active 1 ACC fixed (ACC set to nominal value) CHRBW D1 D0 PAL 0 0 wide 0 1 medium 1 0 reserved 1 1 small Subaddress ...

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SDA 9489X SDA 9589X Subaddress 10h SATNR D7 stabilizes the horizontal PLL for bad satellite signals („fishes“) 0 disabled 1 enabled FMACTI D6 sets the inset condition for the activation of the frame mode 0 frame mode only active for ...

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SDA 9489X SDA 9589X BLKLR adjusts the pedestal level of the OUT1 channel in steps of 0.5LSB pedestal .. +7.5LSB offset Subaddress 12h BRTADJ ...

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SDA 9489X SDA 9589X REFINT D6 changes the refresh rate of eDRAM 0 normal refresh 1 fast refresh BLKINVR D5 inverts the sign of the OUT1 channel offset (BLKLR) 0 offset added during the active picture 1 offset added during ...

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SDA 9489X SDA 9589X Subaddress 14h PKLR Subaddress 15h PKLG ...

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SDA 9489X SDA 9589X Subaddress 16h PKLB Subaddress 17h MAT D7 D6 selects the RGB matrix coefficients for YUV to ...

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SDA 9489X SDA 9589X Subaddress 18h OUTFOR D7 switches between RGB output and YUV output 0 RGB output signals, matrix active 1 YUV output signals UVPOLAR D6 switches between UV or inverted UV output, has no influence in RGB mode ...

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SDA 9489X SDA 9589X BGV D5-D4 adjusts the V background color component the values gives the two MSBs of the V background signal FRV D3-D0 adjusts the V frame color component the value gives the 4 MSBs of the V ...

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SDA 9489X SDA 9589X Subaddress 1Bh XDSCLS ...

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SDA 9489X SDA 9589X MPIPBG D6 selects the background color for multi-PIP mode 0 black 1 same as background color SERVICE D5 selects data service for slicing 0 Closed Caption 1 Widescreen Signalling (WSS) SELLNR D4 D3 line number of ...

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SDA 9489X SDA 9589X Subaddress 1D PIPBLK D2 blanks the current picture by setting it to background color 0 no blank 1 blanks the current selected (WRPOS) PIP PALIDL D1 D0 sensitivity of identification of PAL/NTSC signals 0 0 high ...

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SDA 9489X SDA 9589X Subaddress 1Fh VSHRNK ... Subaddress 20h HSHRNK ... ...

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SDA 9489X SDA 9589X Subaddress 22h PIPHLT D7 highlights the current selected (WRPOS) PIPr 0 no highlighting 1 highlighting the PIP ABRTHD threshold adjustment for reduction of luminance magnitude ABR off 0 ...

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SDA 9489X SDA 9589X DISPMOD ... WIPESP D1 D0 selects the period for opening/closing the PIP window 0 0 wipe off 0 1 1/3 second 1 ...

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SDA 9489X SDA 9589X WRPOS position of the current written picture first writing position = first picture number of last valid writing second writing position .. 1 0 ...

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SDA 9489X SDA 9589X CHRBGY D3 D2 character background luminance level (IRE CHRBGON D1 D0 defines the characters’ background character background (transparent mode ...

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SDA 9489X SDA 9589X CHRADR Subaddress 27h CHRCLR D7 resets ...

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SDA 9489X SDA 9589X PIPSTAT D6 indication of visibility of PIP, corresponds to PIPON 0 PIP off 1 PIP on SYNCST D5 D4 inset synchronization PLL not locked to CVBS signal locked to ...

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SDA 9489X SDA 9589X Subaddress 2Ah DATAA D7-D0 first word of sliced data MSB LSB Subaddress 2Bh DATAB D7-D0 second word of sliced data MSB LSB Subaddress 2Ch DEVICE Micronas PIP IC ...

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SDA 9489X SDA 9589X DATAV D1 new data indication, used for data flow control (polling mode) 0 data read via I 1 new data received and available in DATAA and DATAB SLFIELD D0 DATAA and DATAB are from 0 first ...

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SDA 9489X SDA 9589X 7 Pin Description pin 1 (XIN) 2 (XQ) XIN 3 (HSP) 4 (VSP VSP 5 (SDA) 6 (SCL) SDA SCL 9 (I2C) Micronas schematic VDD VDD VDD VDD slope control VDD ...

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SDA 9489X SDA 9589X pin 10 (INT VDD (IN1 IN2 IN3) IN1 IN2 IN3 14 (FSW) FSW 15 (SEL) Micronas schematic VDD INT + - VDD VDD SEL Preliminary Data Sheet Pin Description remark ...

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SDA 9489X SDA 9589X pin 16 (OUT3) 17 (OUT2) 18 (OUT1) 21 (VREFH) VDD 25 (VREFL) 27 (VREFM) VREFH 24 (CVBS3) VDD VDD 26 (CVBS2) CVBS1 28 (CVBS1) CVBS2 CVBS3 Micronas schematic UT1 O UT2 O UT3 ...

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SDA 9489X SDA 9589X 8 Absolute Maximum Ratings Parameter Ambient Temperature Storage Temperature Junction Temperature Soldering Temperature Input Voltage Output Voltage Supply Voltages Supply Voltage Differentials Total Power Dissipation Latch-Up Protection ESD robustness All voltages listed are referenced to ground ...

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SDA 9489X SDA 9589X 9 Recommended Operating Range Parameter Symbol Supply Voltages V Ambient Temperature Main horizontal / vertical Sync Inputs: VSP, HSP HSP Signal Frequency HSP Signal Frequency HSP Signal Frequency HSP Signal Rise Time HSP Signal High Time ...

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SDA 9489X SDA 9589X Parameter Symbol Input Voltage Range at inputs CVBS1-3 Reference Voltages:VREFL, VREFM, VREFH Reference Voltage Low V Reference Voltage V Middle Reference Voltage High V RGB/YUV Switch:IN1,IN2,IN3,FSW Input Coupling Capacitors Source Resistance Input Voltage Range at inputs ...

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SDA 9489X SDA 9589X Parameter Symbol SCL High Time Set-Up Time DATA t SU;DAT Hold Time DATA t HD;DAT SDA/SCL Rise/Fall Times Set-Up Time Stop t SU;STO Condition Capacitive Load/Bus Line I²C Bus Inputs/Output: SDA, SCL High-Level Input Voltage Low-Level ...

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SDA 9489X SDA 9589X Parameter Symbol Load Capacitance Series resonance resistance Motional capacitance Parallel capacitance In the operating range the functions given in the circuit description are fulfilled. Micronas Recommended Operating Range Limit Values min. typ ...

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SDA 9489X SDA 9589X 10 Characteristics (Assuming Recommended Operating Conditions) Parameter Symbol Average total supply current All Digital Inputs (TTL, I²C) Input Capacitance Input Leakage Current SEL High-Level Output Voltage High-Level Output Voltage Low-Level Output Voltage FSW Low-Level Input Voltage ...

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SDA 9489X SDA 9589X Parameter Symbol Output Fall Time from min max Analog Inputs CVBS1, CVBS2, CVBS3 CVBS Input Leakage Current CVBS Input Capacitance Input Clamping Error Input Clamping Current max. Input Clamping |I Current ...

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SDA 9489X SDA 9589X Parameter Symbol Output Voltage Deviation of OUT1-3 (matching) Contrast Increase αCON αAMP Output Amplitude Ratio ( Brightness Increase Pedestal Level variation RGB / YUV switch; IN1, IN2, IN3 Input Voltage Range ...

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SDA 9489X SDA 9589X Parameter Symbol Horizontal PLL pull-in- range Amplitude of synchronization pulse length of horizontal synchronization pulse length of vertical synchronization pulse ACC range CR AGC range CR Chroma PLL pull-in- range Data slicer Data level Data height ...

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SDA 9489X SDA 9589X 11 Diagrams Figure 11-1 Display mode 0 with picture sizes 1/4 and 1/9 Figure 11-2 Display mode 0 with picture sizes 1/16 and 1/36 Micronas Preliminary Data Sheet Diagrams 11-91 ...

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SDA 9489X SDA 9589X Figure 11-3 Display mode 0 (with scaling) and display mode 11 Figure 11-4 Display mode 2 and 3 (all pictures with same content Figure 11-5 Display modes 4 and 5 Micronas Preliminary Data Sheet ...

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SDA 9489X SDA 9589X 0 1 Figure 11-6 Display modes 6 and Figure 11-7 Display modes 8 and Figure 11-8 Display modes 9 and 10 Micronas ...

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SDA 9489X SDA 9589X Figure 11-9 Display modes 13 and Figure 11-10 Display modes 15 and 16 0 ...

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SDA 9489X SDA 9589X Display mode 20 (Double Window 1) and 19 (Double Window 1.5) Figure 11-12 Combination of display modes 17/ 18 and 9/ 10 (dual PiP application) Figure 11-13 Display modes 19 and 20 (dual PiP application) Micronas ...

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SDA 9489X SDA 9589X 0000001=01 0000010=02 0000011=03 0001001=09 0001011=0B 0001010=0A 0101010=2A 0101011=2B 0101101=2D 0110100=34 0110101=35 0110110=36 0111110=3E 0111111=3F 1000001=41 1000111=47 1001000=48 1001001=49 1010000=50 1010001=51 1001111=4F 1010111=57 1011000=58 1011001=59 Figure 11-14 OSD Character Set Micronas 0000100=04 0000101=05 0000110=06 0100000=20 0100011=23 0100001=21 ...

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SDA 9489X SDA 9589X CVBS 1 TUNER1 CVBS 2 CVBS 3 CVBS 1 TUNER2 Figure 11-15 General Application with 3 CVBS sources and Teletext-Processor CVBS 1 TUNER2 Figure 11-16 General Application with YUV source from DVD Micronas ...

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SDA 9489X SDA 9589X 1/4 PiP frequency [MHz] YPEAK = '010' YPEAK = '100' YPEAK = '111' 1/16 PiP ...

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SDA 9489X SDA 9589X 1/4 PiP frequency [MHz] YPEAK = '010' YPEAK = '100' YPEAK = '111' 1/16 PiP ...

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SDA 9489X SDA 9589X 0.25 0.5 0.75 1 1.25 1.5 frequency [MHz] 1/4 PiP 1/9 PiP 1/16 PiP 1/36 PiP 0.25 0.5 0.75 1 1.25 1.5 ...

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SDA 9489X SDA 9589X 12 Application Circuit Y CVBS1 CVBS1 U Y CVBS2 CVBS3 27p C2 * 20.25 MHz 27p 100 SDA R2 100 SCL +3. +3.3V ...

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SDA 9489X, SDA 9589X Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-562-1PD 102 PRELIMINARY DATA SHEET All information and data contained ...