lxt972a Intel Corporation, lxt972a Datasheet - Page 20

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lxt972a

Manufacturer Part Number
lxt972a
Description
3.3v Dual-speed Fast Ethernet Transceiver Datasheet
Manufacturer
Intel Corporation
Datasheet

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LXT972A — 3.3V Dual-Speed Fast Ethernet Transceiver Datasheet
3.3
3.3.1
3.3.2
3.3.2.1
3.3.2.2
20
Force Interrupt
1. Interrupt (Event) Status Register is cleared on read.
Event X Mask Reg
Event X Status Reg
Figure 5. Interrupt Logic
Per Event
. .
.
Operating Requirements
Power Requirements
The LXT972A requires three power supply inputs (VCCD, VCCA, and VCCIO). The digital and
analog circuits require 3.3V supplies (VCCD and VCCA). These inputs may be supplied from a
single source. Each supply input must be decoupled to ground.
An additional supply may be used for the MII (VCCIO). The supply may be either +2.5V or
+3.3V. Also, the inputs on the MII interface are tolerant to 5V signals from the controller on the
other side of the MII interface. Refer to
As a matter of good practice, these supplies should be as clean as possible.
Clock Requirements
External Crystal/Oscillator
The LXT972A requires a reference clock input that is used to generate transmit signals and recover
receive signals. It may be provided by either of two methods: by connecting a crystal across the
oscillator pins (XI and XO), or by connecting an external clock source to pin XI. The connection of
a clock source to the XI pin requires the XO pin to be left open. A crystal-based clock is
recommended over a derived clock (i.e., PLL-based) to minimize transmit jitter. Refer to the
LXT971A/972A Design and Layout Guide for a list of recommended clock sources.
A crystal is typically used in NIC applications. An external 25 MHz clock source, rather than a
crystal, is frequently used in switch applications. Refer to
requirements
MDIO Clock
The MII management channel (MDIO) also requires an external clock. The managed data clock
(MDC) speed is a maximum of 8 MHz. Refer to
AND
Interrupt Enable
OR
NAND
Table 19 on page 45
Table 32 on page 53
Interrupt Pin
Table 20 on page 45
for MII I/O characteristics.
(MDINT)
for details.
for clock timing
Datasheet

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