AD660SQ/883B AD [Analog Devices], AD660SQ/883B Datasheet - Page 6

• Manufacturer Part Number: AD660SQ/883B
• Description: Monolithic 16-Bit Serial/Byte DACPORT
• Manufacturer: AD [Analog Devices]

AD660
SIGNAL-TO-NOISE RATIO: The signal-to-noise ratio is de-
fined as the ratio of the amplitude of the output when a full-
scale signal is present to the output with no signal present. This
is measured in dB.
DIGITAL-TO-ANALOG GLITCH IMPULSE: This is the
amount of charge injected from the digital inputs to the analog
output when the inputs change state. This is measured at half
scale when the DAC switches around the MSB and as many
as possible switches change state, i.e., from 011 . . . 111 to
100 . . . 000.
DIGITAL FEEDTHROUGH: When the DAC is not selected
(i.e., CS is held high), high frequency logic activity on the digi-
tal inputs is capacitively coupled through the device to show up
as noise on the V
THEORY OF OPERATION
The AD660 uses an array of bipolar current sources with MOS
current steering switches to develop a current proportional to
the applied digital word, ranging from 0 to 2 mA. A segmented
architecture is used, where the most significant four data bits are
thermometer decoded to drive 15 equal current sources. The
lesser bits are scaled using a R-2R ladder, then applied together
with the segmented sources to the summing node of the output
amplifier. The internal span/bipolar offset resistor can be con-
nected to the DAC output to provide a 0 V to +10 V span, or it
can be connected to the reference input to provide a –10 V to
+10 V span.
ANALOG CIRCUIT CONNECTIONS
Internal scaling resistors provided in the AD660 may be con-
nected to produce a unipolar output range of 0 V to +10 V or a
bipolar output range of –10 V to +10 V. Gain and offset drift
are minimized in the AD660 because of the thermal tracking of
the scaling resistors with other device components.
UNIPOLAR CONFIGURATION
The configuration shown in Figure 3a will provide a unipolar
0 V to +10 V output range. In this mode, 50
between the span/bipolar offset terminal (Pin 22) and V
REF IN
LDAC
HBE
SER
CLR
Figure 2. AD660 Functional Block Diagram
UNI/BIP CLR/
16
17
18
19
23
LBE
15
CONTROL
LOGIC
OUT
CS
14
10k
pin. This noise is digital feedthrough.
REF OUT
+10V REF
SIN/
DB0
24
12
16-BIT LATCH
16-BIT LATCH
16-BIT DAC
MSB/LSB/
DB1
11
–V
1
EE
DB7
5
+V
2
CC
+V
AD660
3
LL
10.05k
10k
DGND
resistors are tied
4
13
21
22
20
AGND
OUT
S
SPAN/
BIP
OFFSET
V
OUT
OUT
–6–
(Pin 21), and between REF OUT (Pin 24) and REF IN (Pin
23). It is possible to use the AD660 without any external compo-
nents by tying Pin 24 directly to Pin 23 and Pin 22 directly to
Pin 21. Eliminating these resistors will increase the gain error by
0.25% of FSR.
If it is desired to adjust the gain and offset errors to zero, this can
be accomplished using the circuit shown in Figure 3b. The ad-
justment procedure is as follows:
STEP 1 . . . ZERO ADJUST
Turn all bits OFF and adjust zero trimmer, R4, until the output
reads 0.000000 volts (1 LSB = 153 V).
STEP 2 . . . GAIN ADJUST
Turn all bits ON and adjust gain trimmer, R1, until the output is
9.999847 volts. (Full scale is adjusted to 1 LSB less than the
nominal full scale of 10.000000 volts).
Figure 3b. 0 V to +10 V Unipolar Voltage Output with Gain
and Offset Adjustment
REF IN
LDAC
HBE
SER
CLR
LDAC
HBE
SER
CLR
R1 100
Figure 3a. 0 V to +10 V Unipolar Voltage Output
16
17
18
19
UNI/BIP CLR/
23
R1 50
16
17
18
19
23
UNI/BIP CLR/
REF IN
LBE
CONTROL
15
LOGIC
LBE
CONTROL
15
REF OUT
LOGIC
10k
CS
14
REF OUT
CS
14
+10V REF
10k
DB0
SIN/
24
12
+10V REF
16-BIT LATCH
16-BIT LATCH
16-BIT DAC
SIN/
DB0
24
MSB/LSB/
DB1
12
11
16-BIT LATCH
16-BIT LATCH
16-BIT DAC
–V
MSB/LSB/
DB1
11
1
EE
–V
DB7
1
EE
5
+V
2
DB7
CC
5
+V
2
CC
+V
AD660
3
10k
10.05k
LL
+V
AD660
3
LL
DGND
10.05k
BIP OFF
10k
4
SPAN/
DGND
4
13
21
22
20
S
13
22
20
21
AGND
OUT
R3 16k
OUTPUT
R2
50
S
V
SPAN/
BIP OFF
AGND
OUT
OUT
OUTPUT
REV. A
+V
–V
R2
50
CC
EE
R4
10k