AD671KD-500 AD [Analog Devices], AD671KD-500 Datasheet

no-image

AD671KD-500

Manufacturer Part Number
AD671KD-500
Description
Monolithic 12-Bit 2 MHz A/D Converter
Manufacturer
AD [Analog Devices]
Datasheet
a
PRODUCT DESCRIPTION
The AD671 is a high speed monolithic 12-bit A/D converter
offering conversion rates of up to 2 MHz (500 ns conversion
time). The combination of a merged high speed bipolar/CMOS
process and a novel architecture results in a combination of
speed and power consumption far superior to previously avail-
able hybrid implementations. Additionally, the greater reliability
of monolithic construction offers improved system reliability
and lower costs than hybrid designs.
The AD671 uses a subranging flash conversion technique, with
digital error correction for possible errors introduced in the first
part of the conversion cycle. An on-chip timing generator pro-
vides strobe pulses for each of the four internal flash cycles and
assures adequate settling time for the interflash residue ampli-
fier. A single ENCODE pulse is used to control the converter.
The performance of the AD671 is made possible by using high
speed, low noise bipolar circuitry in the linear sections and low
power CMOS for the logic sections. Analog Devices’ ABCMOS-1
process provides both high speed bipolar and 2-micron CMOS
devices on a single chip. Laser trimmed thin-film resistors are
used to provide accuracy and temperature stability.
The AD671 is available in two conversion speeds and perfor-
mance grades. The AD671J and K grades are specified for op-
eration over the 0 C to +70 C temperature range. The AD671S
grades are specified for operation over the –55 C to +125 C
temperature range. All grades are available in a 0.300 inch wide
24-pin ceramic DIP. The J and K grades are also available in a
24-pin plastic DIP.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FEATURES
12-Bit Resolution
24-Pin “Skinny DIP” Package
Conversion Time: 500 ns max—AD671J/K/S-500
Conversion Time:
Low Power: 475 mW
Unipolar (0 V to +5 V, 0 V to +10 V) and Bipolar Input
Twos Complement or Offset Binary Output Data
Out-of-Range Indicator
MIL-STD-883 Compliant Versions Available
Ranges ( 5 V)
750 ns max—AD671J/K/S-750
PRODUCT HIGHLIGHTS
1. The AD671 offers a single chip 2 MHz analog-to-digital
2. Input signal ranges are 0 V to +5 V and 0 V to +10 V unipo-
3. The external +5 V reference can be chosen to suit the dc ac-
4. Output data is available in unipolar, bipolar offset or bipolar
5. An OUT OF RANGE output bit indicates when the input
6. The AD671 is available in versions compliant with the MIL-
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
conversion function in a space saving 24-pin DIP.
lar, and –5 V to +5 V bipolar, selected by pin strapping. In-
put resistance is 1.5 k . Power supplies are +5 V and –5 V,
and typical power consumption is less than 500 mW.
curacy and temperature drift requirements of the application.
twos complement binary format.
signal is beyond the AD671’s input range.
STD-883. Refer to the Analog Devices Military Products
Databook or current AD671/883B data sheet for detailed
specifications.
FLASH
3-BIT
AD671
AIN BPO/UPO
SELECT
20
RANGE
FUNCTIONAL BLOCK DIAGRAM
21
3
DAC
CORRECTION LOGIC
ENCODE REF IN
2 MHz A/D Converter
16
FLASH
3-BIT
Monolithic 12-Bit
19
OTR MSB
3
14
DAC
V
23
CC
13
ACOM
X4
22
8
LATCHES
COARSE
FLASH
4-BIT
V
24
BIT1-12
EE
12 1
4
AD671
Fax: 617/326-8703
V
LOGIC
17
12
LADDER
MATRIX
FLASH
8-BIT
4-BIT
FINE
DAV
15
DCOM
4
18

Related parts for AD671KD-500

AD671KD-500 Summary of contents

Page 1

FEATURES 12-Bit Resolution 24-Pin “Skinny DIP” Package Conversion Time: 500 ns max—AD671J/K/S-500 Conversion Time: 750 ns max—AD671J/K/S-750 Low Power: 475 mW Unipolar ( +10 V) and Bipolar Input Ranges ( 5 V) ...

Page 2

AD671–SPECIFICATIONS ( MIN DC SPECIFICATIONS unless otherwise noted) Parameter RESOLUTION ACCURACY (+25 C) Integral Nonlinearity (INL MIN MAX Differential Nonlinearity (DNL MIN MAX No Missing Codes l Unipolar Offset l Bipolar Zero ...

Page 3

T MIN MAX DC SPECIFICATIONS unless otherwise noted) Parameter RESOLUTION ACCURACY (+25 C) Integral Nonlinearity (INL (J) MIN MAX (S) MIN MAX Differential Nonlinearity (DNL MIN MAX No Missing ...

Page 4

AD671–SPECIFICATIONS DIGITAL SPECIFICATIONS Parameter LOGIC INPUT High Level Input Voltage Low Level Input Voltage High Level Input Current ( LOGIC Low Level Input Current ( Input Capacitance LOGIC OUTPUTS High Level Output Voltage ...

Page 5

... Although the AD671 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV Model Units AD671JD-500 +6.5 Volts AD671KD-500 +0.5 Volts AD671JD-750 +6.5 Volts AD671KD-750 +1.0 Volts AD671SD-500 +6 ...

Page 6

AD671 AD671 PIN DESCRIPTION Symbol Pin Type Name and Function ACOM 22 P Analog Ground. AIN 20 AI Analog Input Signal. BIT1 (MSB Most Significant Bit. BIT2–BIT11 11–2 DO Data Bits 2–11. BIT12 (LSB Least Significant ...

Page 7

DEFINITIONS OF SPECIFICATIONS INTEGRAL NONLINEARITY (INL) Integral nonlinearity refers to the deviation of each individual code from a line drawn from “zero” through “full scale.” The point used as “zero” occurs 1/2 LSB (1.22 mV for span) ...

Page 8

AD671 Upon receipt of an ENCODE command, the first 3-bit flash converts the analog input voltage. The 3-bit result is passed to a correction logic register and a segmented current output DAC. The DAC output is connected through a resistor ...

Page 9

AD586 + OUT NOISE 6 19 REDUCTION 6 C15 21 GND C14 4 Figure 5. AD586 as Reference Input for AD671 GROUNDING AND DECOUPLING RULES Proper ...

Page 10

AD671 it should be trimmed as above, although a different offset can be set for a particular system requirement. This circuit will give ap- proximately offset trim range. The gain trim is done by applying a signal ...

Page 11

MSB OVER = "1" OTR UNDER = "1" MSB Figure 11. Overrange or Underrange Logic OUTPUT DATA FORMAT The AD671 provides both MSB and MSB outputs, delivering data in positive true straight binary for unipolar input ranges and positive true ...

Page 12

AD671 HIGH PERFORMANCE SAMPLE-AND-HOLD AMPLIFIER (SHA) In order to take full advantage of the AD671’s high speed capa- bilities, a sample-and-hold amplifier (SHA) with fast acquisition capabilities and rigid accuracy requirements is essential. One possibility is a hybrid SHA such ...

Page 13

Figure 17. Typical FFT Plot of AD671 and Discrete SHA F = 500 kHz IN MULTICHANNNEL DATA ACQUISITION SYSTEM The AD684, a quad high speed sample-and-hold amplifier is ideally suited for multichannel data acquisition applications. Figure 18 shows a typical ...

Page 14

AD671 AD671 TO ADSP-2100A INTERFACE Figure 19 demonstrates the AD671 to ADSP-2100A interface. The 2100A with a clock frequency of 12.5 MHz can execute an instruction in one 80 ns cycle. The AD671 is configured to per- form continuous time ...

Page 15

Figure 22. PCB Solder Side Layout for Figures 5, 10 and 13 Figure 23. PCB Component Side Layout for Figures 5, 10 and 13 REV. B –15– AD671 ...

Page 16

AD671 PIN 1 SEATING PLANE 0.175 (4.45) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 24-Pin Plastic DIP (Suffix N) 24-Pin Ceramic DIP (Suffix D) 1 1.200 0.012 (30.48 0.31) 0.085 (2.16 0.018 0.002 0.100 0.005 0.05 (1.27) (0.46 0.05) ...

Related keywords