AD671KD-500 AD [Analog Devices], AD671KD-500 Datasheet
AD671KD-500
Related parts for AD671KD-500
AD671KD-500 Summary of contents
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FEATURES 12-Bit Resolution 24-Pin “Skinny DIP” Package Conversion Time: 500 ns max—AD671J/K/S-500 Conversion Time: 750 ns max—AD671J/K/S-750 Low Power: 475 mW Unipolar ( +10 V) and Bipolar Input Ranges ( 5 V) ...
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AD671–SPECIFICATIONS ( MIN DC SPECIFICATIONS unless otherwise noted) Parameter RESOLUTION ACCURACY (+25 C) Integral Nonlinearity (INL MIN MAX Differential Nonlinearity (DNL MIN MAX No Missing Codes l Unipolar Offset l Bipolar Zero ...
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T MIN MAX DC SPECIFICATIONS unless otherwise noted) Parameter RESOLUTION ACCURACY (+25 C) Integral Nonlinearity (INL (J) MIN MAX (S) MIN MAX Differential Nonlinearity (DNL MIN MAX No Missing ...
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AD671–SPECIFICATIONS DIGITAL SPECIFICATIONS Parameter LOGIC INPUT High Level Input Voltage Low Level Input Voltage High Level Input Current ( LOGIC Low Level Input Current ( Input Capacitance LOGIC OUTPUTS High Level Output Voltage ...
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... Although the AD671 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV Model Units AD671JD-500 +6.5 Volts AD671KD-500 +0.5 Volts AD671JD-750 +6.5 Volts AD671KD-750 +1.0 Volts AD671SD-500 +6 ...
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AD671 AD671 PIN DESCRIPTION Symbol Pin Type Name and Function ACOM 22 P Analog Ground. AIN 20 AI Analog Input Signal. BIT1 (MSB Most Significant Bit. BIT2–BIT11 11–2 DO Data Bits 2–11. BIT12 (LSB Least Significant ...
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DEFINITIONS OF SPECIFICATIONS INTEGRAL NONLINEARITY (INL) Integral nonlinearity refers to the deviation of each individual code from a line drawn from “zero” through “full scale.” The point used as “zero” occurs 1/2 LSB (1.22 mV for span) ...
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AD671 Upon receipt of an ENCODE command, the first 3-bit flash converts the analog input voltage. The 3-bit result is passed to a correction logic register and a segmented current output DAC. The DAC output is connected through a resistor ...
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AD586 + OUT NOISE 6 19 REDUCTION 6 C15 21 GND C14 4 Figure 5. AD586 as Reference Input for AD671 GROUNDING AND DECOUPLING RULES Proper ...
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AD671 it should be trimmed as above, although a different offset can be set for a particular system requirement. This circuit will give ap- proximately offset trim range. The gain trim is done by applying a signal ...
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MSB OVER = "1" OTR UNDER = "1" MSB Figure 11. Overrange or Underrange Logic OUTPUT DATA FORMAT The AD671 provides both MSB and MSB outputs, delivering data in positive true straight binary for unipolar input ranges and positive true ...
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AD671 HIGH PERFORMANCE SAMPLE-AND-HOLD AMPLIFIER (SHA) In order to take full advantage of the AD671’s high speed capa- bilities, a sample-and-hold amplifier (SHA) with fast acquisition capabilities and rigid accuracy requirements is essential. One possibility is a hybrid SHA such ...
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Figure 17. Typical FFT Plot of AD671 and Discrete SHA F = 500 kHz IN MULTICHANNNEL DATA ACQUISITION SYSTEM The AD684, a quad high speed sample-and-hold amplifier is ideally suited for multichannel data acquisition applications. Figure 18 shows a typical ...
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AD671 AD671 TO ADSP-2100A INTERFACE Figure 19 demonstrates the AD671 to ADSP-2100A interface. The 2100A with a clock frequency of 12.5 MHz can execute an instruction in one 80 ns cycle. The AD671 is configured to per- form continuous time ...
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Figure 22. PCB Solder Side Layout for Figures 5, 10 and 13 Figure 23. PCB Component Side Layout for Figures 5, 10 and 13 REV. B –15– AD671 ...
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AD671 PIN 1 SEATING PLANE 0.175 (4.45) OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 24-Pin Plastic DIP (Suffix N) 24-Pin Ceramic DIP (Suffix D) 1 1.200 0.012 (30.48 0.31) 0.085 (2.16 0.018 0.002 0.100 0.005 0.05 (1.27) (0.46 0.05) ...