em78p510nso32j/s ELAN Microelectronics Corp, em78p510nso32j/s Datasheet - Page 61

• Manufacturer Part Number: em78p510nso32j/s
• Description: 8-bit Microprocessor With Otp Rom
• Manufacturer: ELAN Microelectronics Corp

Product Specification (V1.1) 01.25.2008
(This specification is subject to change without further notice)
6.8 Interrupt
Registers for Interrupt
The EM78P510N has ten interrupt sources as listed below:
This IC has internal interrupts which are falling edge triggered, as follows: TCC timer
overflow interrupt, and two 8-bit upper counter/timer overflow interrupt. If these
interrupt sources change signal from high to low, the RF register will generate a “1” flag
to the corresponding register if RE register is enabled.
RF is the interrupt status register which records the interrupt request in flag bit. RE is
the interrupt mask register. Global interrupt is enabled by ENI instruction and is
disabled by DISI instruction. When one of the interrupts (when enabled) is generated,
it will cause the next instruction to be fetched from address 0003H~001BH according to
the interrupt source.
For EM78P510N, each individual interrupt source has its own interrupt vector as
depicted in Table 7.
Before the interrupt subroutine is executed, the contents of ACC, R3[4:0] and the R5
register will be saved by hardware. After the interrupt service routine is finished, ACC,
R3[4:0] and R5 will be pushed back. While in interrupt service routine, other interrupt
service routine should not be allowed to be executed, so if other interrupts occur in an
interrupt service routine, the hardware will save this interrupt, after which when
interrupt service routine is completed, the next interrupt service routine will be
executed.
R_BANK Address Name
Bank 0
Bank 0
Bank 1
Bank 1
Bank 2
TCC overflow interrupt
External interrupt pin
Watch timer interrupt
Timer 1 overflow interrupt
Timer 2 overflow interrupt
A/D conversion complete interrupt
UART transmit interrupt
SPI transmit/receive interrupt
Low voltage detector
0X0E
0X0F
0X09
0x0E
0x0F
T2CR
EIMR
EISR
IMR
ISR
EXIE
EXIF
Bit 7
T1IE
T1IF
T2IF
R/W
R/W
R/W
R/W
R/W
7
7
LVDIE ADIE
LVDIF ADIF
EXIE
EXIF
Bit 6
T2IE
R/W
R/W
R/W
R/W
R/W
6
6
EXIE
EXIF
Bit 5
R/W
R/W
R/W
R/W
R/W
T2S
8-Bit Microprocessor with OTP ROM
5
5
T2MS1 T2MS0
EXIE
EXIF
SPIIE URTIE EXIE9 EXIE8 TCIE
SPIIF URTIF EXIF9 EXIF8 TCIF
Bit 4
R/W
R/W
R/W
R/W
R/W
4
4
EXIE
EXIF
Bit 3
R/W
R/W
R/W
R/W
R/W
3
3
EXIE
EXIF
Bit 2
T2P2
R/W
R/W
R/W
R/W
R/W
2
2
EM78P510N
EXIE
EXIF
Bit 1
T2P1
R/W
R/W
R/W
R/W
R/W
1
1
EXIE
EXIF
Bit 0
T2P0
R/W
R/W
R/W
R/W
R/W
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