em78p510nso32j/s ELAN Microelectronics Corp, em78p510nso32j/s Datasheet - Page 63

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em78p510nso32j/s

Manufacturer Part Number
em78p510nso32j/s
Description
8-bit Microprocessor With Otp Rom
Manufacturer
ELAN Microelectronics Corp
Datasheet
Product Specification (V1.1) 01.25.2008
(This specification is subject to change without further notice)
The EM78P510N can drive LCD, up to 23 segments and 8 commons that can drive
8×23 dots totally. LCD block is made up of LCD driver, display RAM, segment output
pins, common output pins and LCD operating power supply pins. This circuit can work
on normal mode, green mode and idle mode.
The LCD duty, bias, the number of segment, the number of common and frame
frequency are determined by the LCD controller register.
The basic structure contains a timing control which use the main system clock or
subsystem clock to generate the proper timing for different duty and display access.
The R5 register is command register for LCD driver that include LCD enable/disable,
bias (1/2, 1/3 and 1/4), duty (Static, 1/3, 1/4, 1/8) and LCD frame frequency control.
The register bank 1 R6 is LCD RAM address control register. The register bank 1 R7 is
LCD RAM data buffer. The register bank1 R8 is LCD contrast control and LCD clock
register. The control register is explained below.
6.9.1 R5 LCDCR (LCD Control Register)
Bit 7 (LCDEN): LCD Enable Select Bit
Bit 6 (LCDTYPE): LCD Drive Waveform Type Select Bit
Bits 5~4 (BS1~BS0): LCD Bias Select Bits
Bits 3~2 (DS1~DS0): LCD Duty Select Bits
LCDEN
Bit 7
LCDTYPE
Bit 6
0 : disable LCD Circuit. All common/segment outputs are set to VDD
1 : enable LCD circuit
0 : A type wave
1 : B type wave
Level.
BS1
DS1
Bit 5
0
0
1
BS1
0
0
1
1
Bit 4
BS0
BS0
DS0
0
1
×
0
1
0
1
Bit 3
DS1
8-Bit Microprocessor with OTP ROM
Bit 2
DS0
LCD Bias Select
LCD Duty
1/3 Duty
1/4 Duty
1/8 Duty
1/2 Bias
1/3 Bias
1/4 Bias
Static
LCDF1
Bit 1
EM78P510N
LCDF0
Bit 0
• 57

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