em78p510nso32j/s ELAN Microelectronics Corp, em78p510nso32j/s Datasheet - Page 77

• Manufacturer Part Number: em78p510nso32j/s
• Description: 8-bit Microprocessor With Otp Rom
• Manufacturer: ELAN Microelectronics Corp

Product Specification (V1.1) 01.25.2008
(This specification is subject to change without further notice)
6.11.2 Transmitting
In transmitting serial data, the UART operates as follows:
1. Set the TXE bit of the URC register to enable the UART transmission function.
2. Write data into the URTD register and the UTBE bit of the URC register will be set
3. Then start transmitting.
4. Serially transmitted data are transmitted in the following order from the TX pin.
5. Start bit: one “0” bit is output.
6. Transmit data: 7, 8 or 9 bits data are output from the LSB to the MSB.
7. Parity bit: one parity bit (odd or even selectable) is output.
8. Stop bit: one “1” bit (stop bit) is output.
Mark state: output “1” continues until the start bit of the next transmitted data.
After transmitting the stop bit, the UART generates a TBEF interrupt (if enabled).
6.11.3 Receiving
In receiving, the UART operates as follows:
1. Set RXE bit of the URS register to enable the UART receiving function. The UART
2. Receive data is shifted into the URRD register in the order from LSB to MSB.
3. The parity bit and the stop bit are received. After one character is received, the
4. The UART makes the following checks:
5. Read received data from URRD register. And URBF bit will be cleared by
(a) Parity check: The number of 1 of the received data must match the even or odd
(b) Frame check: The start bit must be 0 and the stop bit must be 1.
(c) Overrun check: The URBF bit of the URS register must be cleared (that means
by hardware.
monitors the RX pin and synchronizes internally when it detects a start bit.
URBF bit of the URS register will be set to 1.
If any checks failed, the URTIF interrupt will be generated (if enabled), and an error
flag is indicated in PRERR, OVERR or FMERR bit. The error flag should be
cleared by software otherwise, URTIF interrupt will occur when the next byte is
received.
hardware.
parity setting of the EVEN bit in the URS register.
the URRD register should be read out) before the next received data is loaded
into the URRD register.
8-Bit Microprocessor with OTP ROM
EM78P510N
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