w89c840af Winbond Electronics Corp America, w89c840af Datasheet
w89c840af
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w89c840af Summary of contents
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... Winbond LAN W89C840AF 100/10Mbps Ethernet Controller -1 - W89C840AF Publication Release Date:October 2000 Revision 1.01 ...
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... Publication Release Date:October 2000 -2 - Revision 1.01 W89C840AF ...
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... W89C840AF is a highly integrated Ethernet LAN controller for both 100BaseT and 10BaseT Ethernet. It provides a host bus interface complying with the PCI local bus specification revision 2.1, and the MII interface complying with the IEEE802.3u standard for easily implementing an Ethernet LAN adapter. The built-in 2K bytes transmit FIFO and 4K bytes receive FIFO, controlled by the on-chip bus master, are designed for improving network performance and reducing the host bus utilitzation ...
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... PMEB 119 VCC 120 GND 121 AD31 122 AD30 123 AD29 124 AD28 125 AD27 126 AD26 127 AD25 128 AD24 Fig 1: W89C840AF pin configuration W89C840AF Publication Release Date:October 2000 -4 - Revision 1.01 W89C840AF 64 BTADD0 63 GND 62 VCC 61 BTADATA7 60 BTADATA6 59 BTADATA5 58 BTADATA4 57 EEDO/BTADATA3 ...
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... PCI bus master PCI bus slave controller configuration registers Fig. 2 W89C840AF Block Diagram System Diagram ...
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... When asserted(active low), all PCI output pins of W89C840AF will be in high impedance state, and all open drain signals will be floated. The configurations inside W89C840AF will be in its initial state. This signal must be asserted for a period of at least 10 PCI clocks to correctly take effect of a reset on hardware. ...
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... PCI Request: Asserted by W89C840AF to request bus ownership. REQB will be tri-stated when RSTB asserted. PCI Grant: Asserted by host to grant that W89C840AF have got the bus ownership. When RSTB asserted, W89C840AF will ignore GNTB. Publication Release Date:October 2000 -7 - Revision 1.01 ...
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... PCI Parity Error: Asserted by the W89C840AF acts the bus master data parity error is detected and the parity error response bit (FCS<6>) is also set, it will set both bits of FCS<24> and C14<13> terminate the current transaction after the current data phase is finished. When W89C840AF acts the target data parity error is detected and the bit FCS< ...
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... MII Transmit enable: It indicates that transmits activity to an external PHY. It will be synchronized with MTXCLK. 94 MII management reference clock the reference clock of MMDIO. Each data bit will be latched at the MMDC rising edge. Publication Release Date:October 2000 -9 - Revision 1.01 W89C840AF ...
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... MII Received data error: This pin is driven by PHY device. It indicates a data conversion error is detected by PHY device. The assertion of MRXER should be lasted for longer than a period of MRXCLK. When MRXER asserted, W89C840AF will report a Receive Error detection and a CRC error. 102 MII Received clock source: This clock is from PHY device ...
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... W89C840AF sets the PME_STS bit in the FPMCSR register setting this bit causes the PMEB signal to be asserted. Assertion of the PMEB signal causes external hardware to be wake up the system. If there is not any power supplying PCI slot and W89C840AF, the PMEB signal will stay at low when W89C840AF adapter card is inserted into PCI slot. ...
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... Register (FWUPCS) and it should be ensure the PME_EN bit is set only when the W89C840AF is in the D3 state. Below table describes the Wake-Up, Power Management Control and Status registers with EEPROM bits that control the PMEB signal. Bit Location FPMCSR<8> PCI configuration space PME_EN FPMCSR< ...
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... The W89C840AF scans for the sequence of 16 duplications address of its node ID. If the W89C840AF detects this sequence it assertion the PMEB signal and is reflected in the Power Management Control and Status Register (FPMCSR) and Wake-Up Control and Status Register (FWUPCS). 2. W89C840AF Power Management State and Wake-Up Operation ...
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... Each descriptor can point to two data buffer addresses to store the received packet data. Though the data buffers are not necessarily be contiguous, the descriptors must be contiguous one after the other. The following figures describe the ring structures of receive descriptor. Publication Release Date:October 2000 -14 - Revision 1.01 W89C840AF ...
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... RX packet data data buffer 2 for storing the 3rd RX packet data data buffer 1 for storing the nth RX packet data data buffer 2 for storing the nth RX packet data ext descriptor pointer_ field. Each descriptor has Publication Release Date:October 2000 -15 - Revision 1.01 W89C840AF ...
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... The following figure describes the mixed mode list, composed of both the ring and the chain structures at the same time. data buffer 1 for storing the first RX packet data data buffer 1 for storing the 2nd RX packet data data buffer 1 for storing the 3rd RX packet data data buffer 1 for storing the nth RX packet data Publication Release Date:October 2000 -16 - Revision 1.01 W89C840AF ...
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... RX packet data skip length between descriptors data buffer 1 for storing the 3rd RX packet data data buffer 1 for storing the nth RX packet data data buffer 2 for storing the nth RX packet data Publication Release Date:October 2000 -17 - Revision 1.01 W89C840AF ...
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... This parallel processing of software and the hardware can improve the system receiving performance significantly. data 4 Kbytes FIFO status control receive DMA PCI state machine master status & control PCI slave Publication Release Date:October 2000 -18 - Revision 1.01 W89C840AF data from MAC controls from MAC ...
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... But, if there is only one descriptor needed for the current incoming packet, all of receiving status will be updated in the unique descriptor. The W89C840AF transmit DMA function performs the data transfer from the host memory through on- chip PCI bus master into the internal 2 Kbytes transmit FIFO. The transmit DMA state machine will request the MAC to send out the data in the FIFO onto the MII ...
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... For consecutively transmitting multiple packets, the software driver can previously program all the packet data in the host memory and then release the access right to the W89C840AF. Once the transmit DMA is turned on, the DMA will transmit all of the packet out automatically. The inter-frame gap between these packets will be specified by the MAC block for complying with the IEEE802 ...
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... Media Access Control function (MAC) The function of W89C840AF MAC fully meets the requirements, defined by the IEEE802.3u specification. The following paragraphs will describe the frame structure and the operation of the transmission and receive ...
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... The W89C840AF categorizes the input stream from media into three types of frame. These three types are the packet with uni-cast destination address, the multicast destination address and the broadcast destination address ...
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... CRC. Loopback diagnostics function The loopback mode defined for W89C840AF is used for diagnostic. The transmit out data will appear on the MII interface and will then be fed back into the internal receive channel of the MAC block and then be ...
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... Full duplex and half duplex function The transmit DMA and the receive DMA are independently operating no matter what the W89C840AF is set in full duplex mode or in half duplex mode. However, in MAC side, the operations are different and depends on the full duplex or half duplex mode is selected. ...
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... EEPROM. Another identification register is the F40/FSR, a read only, too. The signature code for Winbond W89C840AF is built in the F40/FSR signature register. The 12Hth and 9aHth bytes will be read out recursively when a number of consecutive PCI configuration space read operation is accessed to the F40/FSR. ...
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... ROM device will be mapped into the host memory by the system BIOS (Basic Input/Output System). After power-on reset, The BIOS will write a set of value with all 1 to the F30/FERBA configuration register and then read the value back. The W89C840AF will return the all 1 value, except some bits with 0, Low Byte (BIT 7 ~ BIT 0) ...
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... F30/FERBA and the bit 1 of F04/FCS are set to high at the same time. the on-board boot ROM data will be fetched by W89C840AF and loaded into the host memory. On the other hand , the address decoder will be disabled if the bit 0 of F30/FERBA is reset to 0. Under this case, W89C840AF will ignore the C48/CBRCR, no matter what content it has ...
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... For the writing operation, the software driver should not start up the next write data request until the bit 13 of C24/CMIIR is reset the W89C840AF. For the read operation, the read data will be valid only if the bit 14 of the register C24/CMIIR is reset the W89C840AF. ...
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... The W89C840AF uses only one interrupt pin, INTA#. However, the interrupt line resource assignment is determined by the system BIOS by writing the related data into the bits the register F3C/FIR in the W89C840AF. The data written into the bits0 the register F3C/FIR can be used by the driver program to decide the interrupt service subroutine configuring. ...
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... FWF1BM1 F70 FWF2BM0 F74 FWF2BM1 F78 FWF3BM0 F7c FWF3BM1 Fdc FPMC Fe0 FPMCSR The initial value of the W89C840AF PCI configuration registers after hardware reset and software reset is listed as following table. Code Abbr. F00 FID F04 FCS F08 FRE F0C FLT F10 ...
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... PCI activity, and the other is the status register (FCS[31:16]) which shows the status information of PCI event. Writing 00h to the command registers will put W89C840AF logically isolated from all PCI access except configuration access. Writing 1 to the bits of the status register will clear them; writing 0 has no effect. ...
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... This bit and bit 6 must be set 1 to signal SERR event. Reserved. Fixed at 0. Parity Error Response. Set PER to high to enable the W89C840AF to respond to parity error. When PER is reset, the W89C840AF will ignore any parity error and continue the normal operation. ...
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... R --- R/W IOS F08/FREV Device Revision Register This register, a read-only with built-in code, shows W89C840AF revision number and its class code. Bit Attribute Bit name 31: 23: 15 7:0 R REV F0C/FLT Latency Timer Register This register specify the W89C840AF master bus latency timer. ...
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... R/W BMA 6:1 R --- 0 R MEM F2C/FSSID Subsystem ID Register This register is loaded from the external EEPROM. The W89C840AF will issue a Retry signals to host when the host tries to access to this register while the EEPROM auto-loading is not yet completed. Bit Attribute Bit name 31:16 R SBID 15:0 R SBVID F30/FERBA Expansion ROM Base Address Register This register is written by power-on software to specify the on-board boot ROM base address in the system ...
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... CAPPR F3C/FIR Interrupt Register The upper half of this register is loaded from external serial EEPROM while the lower half is W89C840AF will issue a Retry signals to host when the host tries to access to this register while the EEPROM auto- loading is not yet completed. Bit Attribute ...
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... R/W ILINE F40/FSR Signature Register(Offset + 40H) Value after Hard-Reset: The F40/FSR register is designed for identifying the hardware of W89C840AF. Bit Attribute Bit name 31:16 R/W DVAR 15:8 R --- 7:0 R SIG F48/FWUPCS Wake-Up Control and Status Register (Offset + 48H) Value after Hard-Reset: Bit Attribute Bit name 31 R/W PMCSP 30 R/W RWUL ...
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... After Hard-Reset, if PMCSP=1 and RWUL=0 then MGPE is cleared to 0. After Hard-Reset, if PMCSP=0 then MGPE is fixed at 0. 00000000H Description Offset address for Wake-Up Frame 3 match Offset address for Wake-Up Frame 2 match Offset address for Wake-Up Frame 1 match Offset address for Wake-Up Frame 0 match Publication Release Date:October 2000 -37 - Revision 1.01 W89C840AF ...
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... CRC value for Wake-Up Frame 2 match Description CRC value for Wake-Up Frame 3 match 00000000H Description Wake-Up Frame 0 Byte-Mask 0 The bit 0 is the byte 0 mask of Wake-Up Frame 0. --- The bit 31 is the byte 31 mask of Wake-Up Frame 0. 00000000H Publication Release Date:October 2000 -38 - Revision 1.01 W89C840AF ...
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... The bit 0 is the byte 32 mask of Wake-Up Frame 1. --- The bit 31 is the byte 63 mask of Wake-Up Frame 1. 00000000H Description Wake-Up Frame 2 Byte-Mask 0 The bit 0 is the byte 0 mask of Wake-Up Frame 2. --- The bit 31 is the byte 31 mask of Wake-Up Frame 2. 00000000H Publication Release Date:October 2000 -39 - Revision 1.01 W89C840AF ...
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... The bit 0 is the byte 0 mask of Wake-Up Frame 3. --- The bit 31 is the byte 31 mask of Wake-Up Frame 3. 00000000H Description Wake-Up Frame 3 Byte-Mask 1 The bit 0 is the byte 32 mask of Wake-Up Frame 3. --- The bit 31 is the byte 63 mask of Wake-Up Frame 3. 5a010001H Description Publication Release Date:October 2000 -40 - Revision 1.01 W89C840AF ...
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... Fixed at 001B. The W89C840A complies with Revision 1.0 of the PCI Power Management Interface Specification. Next Item Pointer. Fixed at 00H. There are no additional items in the Capabilities List. Capability Identifier. Fixed at 01H. This linked list item is the PCI Power Management registers. 00000000H Description Fixed at 0. Publication Release Date:October 2000 -41 - Revision 1.01 W89C840AF ...
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... Burst access to the W89C840AF register will be terminated after 1st data transfer completed with a Disconnect without Data. 5) S/W reset will have the same effect as done by H/W reset on the W89C840AF register, except for the registers or bits C00<0>, C38, C3c, C40, C44, C48. 6) Any read on the reserved register will be returned with 0 The following table outlined all the control/status registers inside this chip and its offset address, and summarized its function ...
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... Boot ROM Size Configuration C4c CTDAR Current Transmit Descriptor Address C50 CTBAR Current Transmit Buffer Address C54~CFF reserved reserved This table lists the initial state of each register in the W89C840AF after hardware reset and software reset separately. Code Abbr. C00 CBCR C04 CTSDR C08 CRSDR ...
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... C50 CTBAR The detailed function and operation for each register in the W89C840AF will be described in the following paragraph. There are total 21 registers to be described in register code order in this paragraph. The full name of these registers are C00/CBCR Bus Control Register, C04/CTSDR Transmit Start Demand ...
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... When the starting address of the data burst access is not aligned, more specifically, the starting address should be a multiple of some number such etc., the W89C840AF will have the first burst transfer that causes that the next burst access will has the start address aligned. ...
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... R/W SKIP 1 R/W ARB 0 R/W SWR C04/CTSDR Transmit Start Demand Register The register C04/CTSDR is used to request the W89C840AF transmission process. Bit Attribute Bit name Burst Length BL defines the maximum number of the long words that can be transferred within one PCI The burst length configuration is as following. ...
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... W TSD C08/CRSDR Receive Start Demand Register The register C04/CTSDR is used to request the W89C840AF receive process. Bit Attribute Bit name 31:0 W RSD C0C/CRDLA Receive Descriptors List Addresses The register C0C/CRDLA defines the start address of the receive descriptor list. It should be updated only when the receive DMA state machine is staying at the stop state ...
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... The register C10/CTDLA defines the start address of the transmit descriptor list. It should be updated only when the transmission DMA state machine is staying at the stop state. Bit Attribute Bit name 31:2 R/W STL 1:0 R/W MBZ Description Start of Transmit List. Must be written as 0 for long word alignment. Publication Release Date:October 2000 -48 - Revision 1.01 W89C840AF ...
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... Reserved. 1xx Reserved. The meanings of the error type is described as following. * Parity Error --- When W89C840AF operates as a bus master, it can detect a data parity error during a read transaction or sample PERRB asserted on a write transaction if Parity Error Response bit (F04[6]) is set. * Master Abort --- When W89C840AF operates as a bus master, W89C840AF terminates the read or write transaction with master abort ...
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... Reserved. Fixed at 0. Timer Expired. A high indicates the general timer (C2C/CGTR) expired. Transmit Early Interrupt The W89C840AF will has Transmit Early Interrupt status set after the packet to be transmitted is completely transferred into the transmit FIFO if Transmit Early Interrupt On bit of C18/CNCR is set. ...
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... When there is no receive buffer available, this bit is set and the receive process enters the suspend state. When W89C840AF is first initialized, this bit will not be set even if there is no buffer available. It will be set only when there has been any available buffer and no available buffer afterwards. ...
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... Fast Ethernet Select When set, W89C840AF will run in 100 Mbps mode. When reset, W89C840AF run in 10 Mbps mode. To change this bit, the transmit state machine must be in Idle state. The SQE test function will be enabled when FES is reset to low. ...
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... R/W TTH Receive Early Interrupt Threshold During receiving packet, the W89C840AF will assert an interrupt request when the bytes number of the received data, which the receive DMA has moved them into the data buffer, excesses the receive early interrupt threshold. To set this field 00H will disable receive early interrupt function. ...
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... When reset, the W89C840AF works in half duplex mode. In full duplex mode, the W89C840AF can transmit and receive packets at the same time. In half duplex mode, the W89C840AF can only exclusively either transmit or receive. The W89C840AF is not allowed to be programmed in internal loop-back mode when full duplex mode ...
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... The Abnormal Interrupt will be enabled if the AIE is set to high. The Abnormal Interrupt is disabled when the AIE is reset to low. The hardware interrupt will be asserted if both the AIE bit of the C1C/CIMR and the AIR bit of the C14/CISR AIR are set to high. Reserved. Fixed at 0. Publication Release Date:October 2000 -55 - Revision 1.01 W89C840AF ...
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... AIE(bit 15) and TFUE are set to high, otherwise, the Transmit FIFO Underflow Interrupt will be disabled. The hardware interrupt will be asserted if all of the bit AIE in C1C/CIMR, the bit TFUE in C1C/CIMR and the bit IUF in C14/CISR are set to high. Publication Release Date:October 2000 -56 - Revision 1.01 W89C840AF ...
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... This bit is the overflow bit of the receive FIFO Overflow counter. The actual number of the FIFO overflow must be more than the number shown by the bits field RFOC if the MRFO is set to high. This bit will be reset after a read operation Publication Release Date:October 2000 -57 - Revision 1.01 W89C840AF ...
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... FIFO is overflow if the receive DMA can not get sufficient utilizing on PCI bus. This counter will be reset after a read operation. PHYAD REGAD TA DATA AAAAA RRRRR Z0 16 bits AAAAA RRRRR 10 16 bits Publication Release Date:October 2000 -58 - Revision 1.01 W89C840AF IDLE Z Z ...
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... MDC should be programmed as 1 and 0 with equal duty cycle and timing width alternately. The AC timing specification with respect to the MIMDC and MIMDIO should follow the media independent interface(MII) specification defined in IEEE 802.3u. Reserved. Fixed at 0. Publication Release Date:October 2000 -59 - Revision 1.01 W89C840AF .... high impedance(z) Idle Data .... Idle Data ...
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... RDCTL if the bit EESEL(bit 11 in this register) is set. BootROM Write Control. When the bit EESEL (bit 11) is reset, setting this bit will trigger the W89C840AF to perform the on-board boot ROM write operation with the writing address specified by the register C28/CBROA. The one byte write data should be latched by the EEBRD[7:0] before setting the WRCTL high ...
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... R/W EEBRD [33:0] C28/CBROA Boot ROM Offset Address Register The register C28/CBROA is used to specify the read or write address of the external boot ROM when accessing the boot ROM through the register C24/CMIIR of the W89C840AF . Bit Attribute Bit name 31:18 R --- 17:0 R/W BROA C2C/CGTR General Timer Register The C2C/CGTR shows the real time content of the W89C840AF ...
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... R CRDA C34/CRBAR Current Receive Buffer Address Register The register C34/CRBAR shows that the start address of the host memory which will be used by the W89C840AF receive DMA state machine to store the current aligned long word data of the current received frame. Bit Attribute Bit name ...
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... The PAR3 defines the bit 24~31 of the MAC address. Physical Address 2. The PAR2 defines the bit 16~23 of the MAC address. Physical Address 1. The PAR1 defines the bit 8~15 of the MAC address. Physical Address 0. The PAR0 defines the bit 0~7 of the MAC address. Publication Release Date:October 2000 -63 - Revision 1.01 W89C840AF ...
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... Reserved. Fixed at 0. Boot ROM Size Select. The size of the on board boot ROM device is selected by BPS[2:0] as follows. BPS2 BPS1 BPS0 Size ------------------------- ---------------------- Boot ROM 16K 32K 64K 128K 256K Publication Release Date:October 2000 -64 - Revision 1.01 W89C840AF ...
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... C4C/CTDAR Current Transmit Descriptor Address Register The C4C/CTDAR shows that the start address of the descriptor which the W89C840AF transmit DMA state machine is used to process the current frame. Bit Attribute Bit name 31:0 R CTDA C50/CTBAR Current Transmit Buffer Address Register The C50/CTBAR shows that the address of the system memory from which the W89C840AF state machine will fetch the long word data and queue the data into the FIFO for transmission ...
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... RAC Receive Access Control The W89C840AF receive DMA is allowed to access this descriptor if RAC is set to high by the driver program. Otherwise, the driver program will access this descriptor if the RAC is reset to low, i.e. the descriptor 0 allows to be accessed by software driver when set RAC;by hardware when reset RAC. The RAC is valid on each descriptor of the current received frame ...
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... CRC Error (R00[1]) is reset, i.e. no CRC error. This bit is not valid if a late collision (R00[6]) or runt packet (R00[11]) is set. This bit is valid only when RFD (R00[9]) or RLD (R00[8]) is set, i.e. the first or the last descriptor of the current frame. Publication Release Date:October 2000 -67 - Revision 1.01 W89C840AF ...
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... RSZ1 Receive Buffer Size 1. The RSZ1 indicates the size, in bytes, of the first data buffer pointed by the current descriptor. If this field is 0, the W89C840AF will ignore this buffer. The buffer size must be longword aligned. The maximum size of this buffer is 4093 bytes. R02, Receive Descriptor 2 ...
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... TAC Transmit Access Control : When the TAC bit is set, the current descriptor allows to be accessed by W89C840AF, otherwise the W89C840AF can not issue any read or write request on this descriptor. When the TAC is reset to low, the driver program is allowed to access this descriptor. This bit will be reset before completing to fill data into the transmit buffer; set if the data in the transmit buffer is available ...
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... DEF Deferred: When set, it indicates that the W89C840AF had to defer when ready to transmit a frame because the carrier sense input was asserted before the W89C840AF gets the grant to acquire the network media. This bit is valid only when TLD (T01[30]) is set, i.e. when the current descriptor is the last descriptor of the current frame ...
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... FINT Frame Interupt. The W89C840AF will set the Transmit Interrupt bit(bit 0 of C14/CISR) after the current frame was transmitted if the FINT is previously set by the driver program. This bit is valid only when the current descriptor is the first descriptor of the current frame (TFD set). ...
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... PD Padding Disable: The W89C840AF does not add the padding data on a frame shorter than 64 bytes when the PD bit is set to high. However, the W89C840AF will automatically add a padding data on a frame shorter than 64 bytes when the PD bit is reset to low. The four bytes of CRC will be appended at the end of the padding field of the transmitted frame no matter what the ICRC is set or reset if the PD is reset ...
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... +0.5 250 Condition Maximum Vdd=5.25V 150 Vdd=5.25V 250 Condition Maximum 0 +0.5 IoL=4.0mA 0.4 Ioh=-4.0mA Vin=5.25V 10 Vout=Vdd 10 Publication Release Date:October 2000 -73 - Revision 1.01 W89C840AF Unit Unit mA mA Unit ...
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... T3 BE#'s T5 T12 INPUT Min Publication Release Date:October 2000 -74 - Revision 1.01 W89C840AF T11 DATA T4 T6 T13 T10 OUTPUT T14 T15 Typical Max Unit nsec nsec nsec nsec nsec nsec nsec nsec 12 13 nsec 12 13 nsec ...
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... T3 BE#'s T5 T13 INPUT Min Publication Release Date:October 2000 -75 - Revision 1.01 W89C840AF T12 T4 T6 T14 T10 INPUT T15 T16 T18 T17 Typical Max Unit nsec nsec nsec nsec nsec nsec nsec nsec 12 13 nsec 12 13 ...
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... T1,T2 and T3 are used for the disconnect type C(host try to transfer more than one data phase BE#'s T2 Min Publication Release Date:October 2000 -76 - Revision 1.01 W89C840AF nsec nsec 12 13 nsec 12 13 nsec for configuration read Typical Max Unit nsec 12 13 ...
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... Note: 1) The other timing requirements for PCI input signal are as the read transaction timing and T3 are used for the target abort type(host addressing error). AC Characteristics (V DD =4. 5.25V V, BE#'s T2 Publication Release Date:October 2000 -77 - Revision 1.01 W89C840AF Min typical MAX UNIT 0 nsec 11 12 ...
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... AC Characteristics (V DD =4. 5.25V V, T10 T12 T9 T11 Publication Release Date:October 2000 -78 - Revision 1.01 W89C840AF T5 T8 T10 T9 T12 T11 Min typical MAX UNIT nsec 8 13 ...
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... MIN. MAX 210 - 210 MIN, MAX. 210 - 210 - 210 Publication Release Date:October 2000 -79 - Revision 1.01 W89C840AF UNIT UNIT Unit ...
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... Note 1: Load capacitance employed on output is 50 pF. Note 2: SW1=Open for push pull outputs during timing test. MIN 130 0 95 155 10 20 TEST CONDITION 5V+5% 25C/70C GND to 4.0V 5nS 1.5V Float (V) + 0.5V SW1 (Note 2.2K Output CL (Note 1) Publication Release Date:October 2000 -80 - Revision 1.01 W89C840AF MAX. Unit - ...
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... SW1=GND for High-Z to active high and active high to High-Z measurements. Pin Capacitance TA = 25C MHz SYMBOL OUT Derating Factor Output timing is measured with a purely capacitive load of 50pF. The correction factor when CL>50pF is +0,4 ns/pF. $. Package Dimension PARAMETER TYP Input Capacitance 7 Output Capacitance 10 Publication Release Date:October 2000 -81 - Revision 1.01 W89C840AF UNIT pF pF ...
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... Dimension in mm Nom Nom Max Min 0.134 0.10 0.107 0.113 2.57 2.72 0.008 0.010 0.15 0.20 0.006 0.10 0.15 0.010 14.00 13.90 0.551 0.555 20.00 19.90 0.787 0.791 0.020 0.50 0.685 0.677 17.00 17.20 0.921 23.20 0.913 23.00 0.039 0.031 0.60 0.80 0.071 0.063 1.40 1.60 0.003 12 0 Publication Release Date:October 2000 -82 - Revision 1.01 W89C840AF L Detail F 1 Max 3.40 2.87 0.25 0.25 14.10 20.10 17.40 23.40 1.00 1.80 0.08 12 ...