ST10 STMICROELECTRONICS [STMicroelectronics], ST10 Datasheet

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ST10

Manufacturer Part Number
ST10
Description
16-BIT MCU WITH 32K BYTE ROM
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet

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August 1999
This is advance information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
HIGH PERFORMANCE CPU
– 16-BIT CPU WITH 4-STAGE PIPELINE
– 80ns INSTRUCTION CYCLE TIME @ 25MHz CLK
– 400ns 16 X 16-BIT MULTIPLICATION
– 800ns 32 / 16-BIT DIVISION
– ENHANCE D BOOLEAN
– ADDITIONAL INSTRUCTIONS TO SUPPOR T HLL
– SINGLE-CYCL E CONT EXT SWITCHING SUPPORT
MEMORY ORGANIZATION
– 32K BYTE ON-CHIP ROM MEMORY
– UP TO 16M BYTE LINEAR ADDRESS SPACE FOR
– 2K BYTE ON-CHIP INTERNAL RAM (IRAM)
– 2K BYTE ON-CHIP EXTENSION RAM (XRAM)
FAST AND FLEXIBLE BUS
– PROGRAMMABLE
– 8-BIT OR 16-BIT EXTERNAL DATA BUS
– MULTIPLEXED OR DEMULTIPLEXED EXTERNAL
– FIVE PROGRAMMABLE CHIP-SELECT SIGNALS
– HOLD-ACKNOWLEDGE
INTERRUPT
– 8-CHANNEL PERIPHERAL EVENT CONTROLLER
– 16-PRIORITY-LEVEL INTERRUPT SYSTE M WITH
TIMERS
– TWO MULTI-FUNCTIONAL GENERAL PURPOSE
– TWO 16-CHANNEL CAPTURE/COMPARE UNITS
A/D CONVERTER
– 16-CHANN EL 10-BIT
– 7.76 s CONVERSION TIME
FAIL-SAFE PROTECTION
– PROGRAMMABLE WATCHDOG TIMER
– OSCILLATOR WATCHDOG
ON-CHIP CAN 2.0B INTERFACE
ON-CHIP BOOTSTRAP LOADER
CLOCK GENERATION
– ON-CHIP PLL
– DIRECT OR PRESCALE D CLOCK INPUT
FACILITIES
AND OPERATING SYSTEMS
CODE AND DATA (5M BYTE WITH CAN)
CHARA CTERISTICS FOR DIFFERENT ADDRESS
RANGES
ADDRE SS/DATA BUSES
SUPPORT
FOR SINGLE CYCLE, INTERRUPT DRIVEN DATA
TRANSFER
56 SOURCES, SAMPLE-RATE DOWN TO 40ns
TIMER UNITS WITH 5 TIMERS
EXTERNAL
BUS
BIT
MANIPULATION
ARBITRATION
16-BIT MCU WITH 32K BYTE ROM
BUS
16
16
8
XRAM
ROM
Byte
32K
CAN
Port 6
UP TO 111 GENERAL PURPOSE I/O LINES
– INDIVIDUALLY PROGRAMMABLE AS INPUT,
– PROGRAMMABLE DRIVE STRENGTH
– PROGRAMMABLE THRESHOLD (HYSTERESIS)
IDLE AND POWER DOWN MODES
– IDLE CURRENT <95mA
– POWER-DOWN SUPPLY CURRENT <400 A
4-CHANNEL PWM UNIT
SERIAL CHANNELS
– SYNCHRONOUS/ASYN CSERIAL CHANNEL
– HIGH-SPEED SYNCHRON OUS CHANNEL
DEVELOPMENT SUPPORT
– C-COM PILERS, MACRO-ASSEMBLER PACKAGES,
144-PIN PQFP PACKAGE
OUTPUT OR SPECIA L FUNCTION
EMULATORS, EVAL BOARDS, HLL-D EBUGGERS,
SIMULATORS, LOGIC ANALYZER DISASSEM-
BLERS, PROGRAMMING BOARDS
8
32
Port 5
16
16
16
(Plastic Quad Flat Pack)
PQFP144 (28 x 28 mm)
Interrupt Controller
BR G
CPU-Core
Port 3
15
BR G
ST10C167
PEC
Port 7
8
16
16
16
Port 8
OSC.
Watchdog
Internal
8
RAM
1/65
16

Related parts for ST10

ST10 Summary of contents

Page 1

... EMULATORS, EVAL BOARDS, HLL-D EBUGGERS, SIMULATORS, LOGIC ANALYZER DISASSEM- BLERS, PROGRAMMING BOARDS 144-PIN PQFP PACKAGE 32K 32 Byte ROM 16 16 XRAM CAN Port 5 Port ST10C167 16 16 Internal CPU-Core RAM PEC Watchdog Interrupt Controller 16 OSC Port 3 Port 7 Port ...

Page 2

... ST10C167 TABLE OF CONTENTS I INTRODUCTION ......................................................................................................... II PIN DATA .................................................................................................................. III FUNCTIONAL DESCRIPTION.................................................................................... IV MEMORY ORGANIZATION........................................................................................ V CENTRAL PROCESSING UNIT (CPU) ...................................................................... VI EXTERNAL BUS CONTROLLER............................................................................... VII INTERRUPT SYSTEM ................................................................................................ VIII CAPTURE/COMPARE (CAPCOM) UNIT ................................................................... IX GENERAL PURPOSE TIMER UNIT........................................................................... IX.1 GPT1 .......................................................................................................................... IX.2 GPT2 .......................................................................................................................... X PWM MODULE ................ ........................................................................................... XI PARALLEL PORTS ......... ........................................................................................... XII A/D CONVERTER...................................... ................................................................. XIII SERIAL CHANNELS .............................................................................. .................... ...

Page 3

... Phase locked loop ...................................................................................................... XX.4.7 Memory cycle variables .............................................................................................. XX.4.8 External clock drive XTAL1 .......................................... .............................................. XX.4.9 Multiplexed bus ........................................................................................................... XX.4.10 Demultiplexed bus ...................................................................................................... XX.4.11 CLKOUT and READY ................................................................................................. XX.4.12 External bus arbitration ........................................................................... .................... XX.4.13 Highspeed synchronous serial interface (SSC) timing ............................................... XXI PACKAGE MECHANICAL DATA XXII ORDERING INFORMATION ....................................................................................... ........................................................................... ST10C167 Page 3/65 ...

Page 4

... I/O capabilities. of 16-bit It also provides on-chip high-speed RAM and clock generation via PLL Port 0 16-bit Port 1 16-bit Port 2 16-bit ST10C167 Port 3 15-bit Port 4 8-bit Port 6 8-bit Port 7 8-bit Port 8 8-bit ...

Page 5

... P5.1/AN1 29 P5.2/AN2 P5.3/AN3 30 31 P5.4/AN4 32 P5.5/AN5 P5.6/AN6 33 34 P5.7/AN7 35 P5.8/AN8 36 P5.9/AN9 ST10C167 ST10C167 108 P0H.0/AD8 107 P0L.7/AD7 106 P0L.6/AD6 105 P0L.5/AD5 104 P0L.4/AD4 103 P0L.3/AD3 102 P0L.2AD2 101 P0L.A/AD1 100 P0L.0/AD0 99 EA ...

Page 6

... ST10C167 II - PIN DATA (continued) Table 1 : Pin list Symbol Pin Type P6 ... ... P8 I/O 9 I/O ... ... 16 I/O P7 ... ... I/O ... ... 26 I/O P5 P5.10 - P5. 6/65 Function 8-bit bidirectional I/O port, bit-wise programmable for input or output via direction bits ...

Page 7

... Least Significant Segment Address Line P4.5 A21 Segment Address Line CAN_RxD CAN Receive Data Input P4.6 A22 Segment Address Line, CAN_TxD CAN Transmit Data Output P4.7 A23 Most Significant Segment Address Line External Memory Read Strobe activated for every external instruc- tion or data read access. ST10C167 7/65 ...

Page 8

... XTAL2 unconnected. Minimum and maximum high/low and rise/fall times specified in the AC Characteristics must be observed. Reset Input with Schmitt-Trigger characteristics. A low level at this pin for a specified duration while the oscillator is running resets the ST10C167. An internal pullup resistor permits power-on reset using only a capacitor connected to V ...

Page 9

... CPU to vector to the NMI trap routine. If bit PWDCFG = ‘0’ in SYSCON register, when the PWRDN (power down) instruction is exe- cuted, the NMI pin must be low in order to force the ST10C167 to go into power down mode. If NMI is high and PWDCFG =’0’, when PWRDN is executed, the part will continue to run in normal mode ...

Page 10

... Byte XRAM CAN_RXD CAN CAN_TXD Port 5 Port 6 8 10/65 block diagram gives an overview of the different on-chip components and the high bandwidth inter- nal bus structure of the ST10C167. CPU-Core PEC 16 Interrupt Controller BRG BRG Port 7 Port Internal 16 RAM Watchdog XTAL1 OSC ...

Page 11

... The XRAM address range is 00’E000h - 00’E7FFh if the XRAM is enabled (XPEN bit 2 of SYSCON register). As the XRAM appears like external memory, it cannot be used for the ST10C167’s system stack or register banks. The is XRAM is not provided for single bit storage and therefore is not bit addressable. If bit XRAMEN is cleared, then any access in the address range 00’ ...

Page 12

... SFRs. Additional hardware has been added for a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Most of the ST10C167’s instructions can be exe- cuted in one instruction cycle which requires 80ns at 25MHz CPU clock. For example, shift and rotate instructions are processed in one instruc- tion cycle independent of the number of bits to be shifted ...

Page 13

... The active level of the READY pin can be set by bit RDYPOL in the BUSCONx registers. When the READY function is enabled for a specific address window, each bus cycle within the window must be terminated with the active level defined by bit RDYPOL in the associated BUSCON register. ST10C167 13/65 ...

Page 14

... Software interrupts are supported by means of the ‘TRAP’ instruction in combination with an individ- ual trap (interrupt) number. Table 2 shows all the available ST10C167 inter- rupt sources and the corresponding hard- ware-related interrupt flags, vectors, vector locations and trap (interrupt) numbers : ...

Page 15

... SCRIE SCRINT SCEIR SCEIE SCEINT PWMIR PWMIE PWMINT XP0IR XP0IE XP0INT XP1IR XP1IE XP1INT XP2IR XP2IE XP2INT XP3IR XP3IE XP3INT ST10C167 Vector Trap Location Number 00’00C8h 32h 00’00CCh 33h 00’00D0h 34h 00’00D4h 35h 00’00D8h 36h 00’00DCh 37h 00’00E0h 38h 00’00E4h 39h 00’ ...

Page 16

... ST10C167 VII - INTERRUPT SYSTEM (continued) Hardware traps are exceptions or error conditions that arise during run-time. They cause immediate non-maskable system reaction similar to a stan- dard interrupt service (branching to a dedicated vector table location). The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag regis- ...

Page 17

... VIII - CAPTURE/COMPARE (CAPCOM) UNIT The ST10C167 has two 16 channel CAPCOM units. They support generation and control of timing sequences channels with a maximum resolution of 320ns at 25MHz CPU clock. The CAPCOM units are typically used to handle high speed I/O tasks such as pulse and ...

Page 18

... ST10C167 IX - GENERAL PURPOSE TIMER UNIT The GPT unit is a flexible multifunctional timer/ counter structure which is used for time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or pulse multiplication. The GPT unit contains five 16-bit timers organized into two separate modules GPT1 and GPT2 ...

Page 19

... Table 7 lists the timer input frequencies, resolution and periods for each pre-scaler option at 25MHz CPU clock. This also applies to the Gated Timer Mode of T6 and to the auxiliary timer T5 in Timer and Gated Timer Mode. ST10C167 Interrupt Request T3OUT Interrupt Request Interrupt ...

Page 20

... ST10C167 IX - GENERAL PURPOSE TIMER UNIT (continued) Table 7 : GPT2 timer input frequencies, resolution and periods f = 25MHz CPU 000B 001B Pre-scaler factor 4 8 Input Frequency 6.25MHz 3.125MHz 1.563MHz Resolution 160ns 320ns Period 10.49ms 21.0ms Figure 6 : Block diagram of GPT2 T5EUD CPU Clock n 2 n=2...9 T5 ...

Page 21

... Hz 47.68Hz * PPx Period Register Match Comparator * PTx Up/Down/ 16-Bit Up/Down Counter Clear Control Match Comparator Output Control Shadow Register Write Control * PWx Pulse Width Register ST10C167 14-bit 16-bit 1.526KHz 0.381KHz 23.84Hz 5.96Hz 14-bit 16-bit 762.9Hz 190.7Hz 11.92Hz 2.98Hz POUTx Enable 21/65 ...

Page 22

... ST10C167 XI - PARALLEL PORTS The ST10C167 provides up to 111 I/O lines orga- nized into eight input/output ports and one input port. All port lines are bit-addressable, and all input/out- put lines are individually (bit-wise) programmable as input or output via direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when config- ured as inputs ...

Page 23

... The AD converter ST10F168 supports different conversion modes : – Single channel single conversion : the analog level of the selected channel is sampled once and converted. The result of the conversion is stored in the ADDAT register. – ...

Page 24

... ST10C167 XIII - SERIAL CHANNELS Serial communication with other microcontrollers, processors, terminals or external peripheral com- ponents is provided by two serial interfaces: the asynchronous/synchronous serial (ASC0) and the high-speed synchronous serial channel (SSC). Two dedicated Baud rate generators set up all standard Baud rates without the requirement of oscillator tuning ...

Page 25

... High Speed Synchronous Serial Channel (SSC) The High-Speed Synchronous Serial Interface SSC provides flexible high-speed communication between the ST10C167 and other microcontrollers, microprocessors or external peripherals. The SSC supports full-duplex and half-duplex synchronous communication; The serial clock signal can be generated by the SSC itself (master mode received from an external master (slave mode) ...

Page 26

... ST10C167 XIV - CAN MODULE The integrated CAN module handles the com- pletely autonomous transmission and reception of CAN frames in accordance with the CAN specifi- cation V2.0 part B (active) i.e. the on-chip CAN module can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers ...

Page 27

... XVI - INSTRUCTION SET SUMMARY The table below lists the instructions of the ST10C167. The various addressing modes, instruction operation, parameters for conditional Table 13 : Instruction set summary Mnemonic ADD(B) Add Word (Byte) operands ADDC(B) Add Word (Byte) operands with Carry SUB(B) Subtract Word (Byte) operands ...

Page 28

... ST10C167 XVI - INSTRUCTION SET SUMMARY (continued) Table 13 : Instruction set summary (continued) Mnemonic JNBS Jump relative and set bit if direct bit is not set CALLA, CALLI, CALLR Call absolute/indirect/relative subroutine if condition is met CALLS Call absolute subroutine in any code segment PCALL Push direct Word register onto system stack & call absolute subroutine ...

Page 29

... This means that the bidirectional reset transforms an internal watchdog timer reset or software reset into an external hardware reset with a minimum duration of 1024 TCL. The consequence is that during a watchdog timer reset or software reset, the behavior of the ST10C167 is equal to an external hardware reset. ST10C167 can be ...

Page 30

... ST10C167 XVIII - POWER REDUCTION MODES Two different power reduction modes with differ- ent levels of power reduction can be entered under software control. In Idle mode the CPU is stopped, while the peripherals continue their operation. Idle mode can be terminated by any reset or interrupt request. In Power Down mode both the CPU and the peripherals are stopped ...

Page 31

... XIX - SPECIAL FUNCTION REGISTER OVERVIEW Table 14 lists all SFRs which are implemented in the ST10C167 in alphabetical order. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical Address”. ...

Page 32

... ST10C167 XIX - SPECIAL FUNCTION REGISTER OVERVIEW (continued) Table 14 : Special function registers listed by name (continued) Physical Name address address CC8IC b FF88h CC9 FE92h CC9IC b FF8Ah CC10 FE94h CC10IC b FF8Ch CC11 FE96h CC11IC b FF8Eh CC12 FE98h CC12IC b FF90h CC13 FE9Ah CC13IC b FF92h CC14 ...

Page 33

... CPU Data Page Pointer 2 Register (10 bit) 03h CPU Data Page Pointer 3 Register (10 bit) E0h External Interrupt Control Register 3Eh Device Identifier Register 3Fh Manufacturer Identifier Register 3Dh On-chip Memory Identifier Register ST10C167 Reset value 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h ...

Page 34

... ST10C167 XIX - SPECIAL FUNCTION REGISTER OVERVIEW (continued) Table 14 : Special function registers listed by name (continued) Physical Name address address IDPROG F078h E MDC b FF0Eh MDH FE0Ch MDL FE0Eh ODP2 b F1C2h E ODP3 b F1C6h E ODP6 b F1CEh E ODP7 b F1D2h E ODP8 b F1D6h E ONES FF1Eh P0L b FF00h P0H ...

Page 35

... CAPCOM Timer 0 Interrupt Control Register 2Ah CAPCOM Timer 0 Reload Register 29h CAPCOM Timer 1 Register CFh CAPCOM Timer 1 Interrupt Control Register 2Bh CAPCOM Timer 1 Reload Register 20h GPT1 Timer 2 Register ST10C167 Reset value 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h ...

Page 36

... ST10C167 XIX - SPECIAL FUNCTION REGISTER OVERVIEW (continued) Table 14 : Special function registers listed by name (continued) Physical Name address address T2CON b FF40h T2IC b FF60h T3 FE42h T3CON b FF42h T3IC b FF62h T4 FE44h T4CON b FF44h T4IC b FF64h T5 FE46h T5CON b FF46h T5IC b FF66h T6 FE48h T6CON b FF48h T6IC ...

Page 37

... STmicroelectronics Manufacturer (JTAG world- wide normalisation). IDCHIP (F07Ch / 3Eh) ESFR Description IDCHIP: Device Identifier - 0A72h for ST10C167. IDMEM (F07Ah / 3Dh) ESFR Description IDMEM: 1008h for ST10C167 (MCU with ROM). IDPROG (F078h / 3Ch) ESFR Description IDPROG: 0000h for ST10C167 (MCU with ROM). ST10C167 37/65 ...

Page 38

... Absolute Maximum Ratings. SS XX.2 - Parameter interpretation The parameters listed in the following tables represent the characteristics of the ST10C167 and its demands on the system. Where the ST10C167 logic provides signals with their respective timing characteristics, the symbol “CC” 38/65 Parameter -0 > < ...

Page 39

... V IN IHmin ILmax 0 V < V < MHz RSTIN = IH1 [MHz] CPU RSTIN = V IH1 [MHz] CPU 5 ST10C167 Maximum Unit – 0.5 0.2 V – 0 – 0 ...

Page 40

... ST10C167 XX - ELECTRICAL CHARACTERISTICS (continued) Notes 1. This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage results from the external circuitry. 2. The maximum current may be drawn while the respective signal line remains inactive. ...

Page 41

... Partially tested, guaranteed by design characterization. Sample time and conversion time of the ST10C167’s ADC are programmable. The table below should be used to calculate the above timings. Conversion clock t ADCON ...

Page 42

... Notes 1. The external clock input range refers to a CPU clock range of 10...25MHz. 2. The maximum frequency depends on the duty cycle of the external clock signal. 42/65 to generate f CPU when calculating the timings for the ST10C167. . Both CPU The example for PLL operation shown in Figure 11 refers to a PLL factor of 4. ...

Page 43

... XTAL max CPU individual TCLs. The timings listed in the AC Characteristics that refer to TCL therefore must be calculated using the minimum TCL that is possible under the respective circumstances. ST10C167 = f * CPU XTAL the PLL XTAL is constantly adjusted 43/65 ...

Page 44

... ST10C167 XX - ELECTRICAL CHARACTERISTICS (continued) The real minimum value for TCL depends on the jitter of the PLL. The PLL tunes F CPU locked The relative deviation of TCL is XTAL the maximum when it is refered to one TCL period. It decreases according to the formula and to the Figure 12 given below. For N periods of ...

Page 45

... Max. CPU Clock = 25MHz Min. Max – TCL - – TCL - 16 – TCL - – TCL - - – - ST10C167 CPU XTAL N = 1.5/2,/2.5/3/4/5 Unit Min. Max 100 * – – – – ...

Page 46

... ST10C167 XX - ELECTRICAL CHARACTERISTICS (continued) Table 18 : Multiplexed bus characteristics (continued) Symbol Parameter 1 CC Address float after RD (with RW-delay Address float after RD RW-delay RD, WR low time (with RW-delay RD, WR low time (no RW-delay valid data in (with ...

Page 47

... – 3TCL - – 2TCL - 14 – 0 – – – 2TCL - – 2TCL - ST10C167 Unit Max. – ns – ns – ns – ns 2TCL - – ns – ns 47/65 ...

Page 48

... ST10C167 XX - ELECTRICAL CHARACTERISTICS (continued) Figure 14 : External Memory Cycle : multiplexed bus, with/without read/write delay, normal ALE CLKOUT t 5 ALE t 6 CSx t 6 A23-A16 (A15-A8) BHE t Read Cycle 6m Address BUS (P0) RD Write Cycle Address BUS (P0) WR WRL WRH 48/ ...

Page 49

... BUS (P0) RD Write Cycle BUS (P0) WR WRL WRH Address Address ST10C167 Data Data Out t 23 49/65 ...

Page 50

... ST10C167 XX - ELECTRICAL CHARACTERISTICS (continued) Figure 16 : External Memory Cycle: multiplexed bus, with/without read/write delay, normal ALE, read/ write chip select CLKOUT t 5 ALE t 6 A23-A16 (A15-A8) BHE t 6 Read Cycle Address BUS (P0) RdCSx Write Cycle BUS (P0) Address WrCSx 50/ Address t 16 ...

Page 51

... BHE Read Cycle t 6 BUS (P0) Address RdCSx Write Cycle BUS (P0) WrCSx Address Address ST10C167 Data Data Out t 56 51/65 ...

Page 52

... ST10C167 XX - ELECTRICAL CHARACTERISTICS (continued) XX.4.10 - Demultiplexed bus 10 0V -40 to +125 (for Port0, Port1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100pF (for Port 6, CS) = 100pF L ALE cycle time = 4 TCL + Table 19 : Demultiplexed bus characteristics Symbol Parameter t CC ALE high time ...

Page 53

... – 0 – – F – – – - – TCL - ST10C167 Unit Max. – ns 2TCL - 3TCL - – ns – ns – ns – ns 2TCL - TCL - – ...

Page 54

... ST10C167 XX - ELECTRICAL CHARACTERISTICS (continued) Figure 18 : External Memory Cycle: demultiplexed bus, with/without read/write delay, normal ALE CLKOUT t 5 ALE t 6 CSx A23-A16 (A15-A8) BHE Read Cycle Data Bus (P0 Write Cycle Data Bus (P0 WRL WRH 54/ ...

Page 55

... BHE Read Cycle Data Bus (P0) RD Write Cycle Data Bus (P0) WR WRL WRH Address Data Out ST10C167 Data 55/65 ...

Page 56

... ST10C167 XX - ELECTRICAL CHARACTERISTICS (continued) Figure 20 : External Memory Cycle: demultiplexed bus, with/without read/write delay, normal ALE, read/ write chip select CLKOUT t 5 ALE A23-A16 (A15-A8) BHE Read Cycle Data Bus (P0 RdCsx Write Cycle Data Bus (P0 WrCSx 56/ ...

Page 57

... CLKOUT t 5 ALE t 6 A23-A16 (A15-A8) BHE Read Cycle Data Bus (P0) RdCsx Write Cycle Data Bus (P0) WrCSx Address Data Out ST10C167 Data 57/65 ...

Page 58

... ST10C167 XX - ELECTRICAL CHARACTERISTICS (continued) XX.4.11 - CLKOUT and READY 10 0V -40 to +125 (for Port0, Port1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100pF L C (for Port 6, CS) = 100pF L Table 20 : CLKOUT and READY characteristics Symbol Parameter t CC CLKOUT cycle time CLKOUT high time ...

Page 59

... For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC waitstate this delay is zero. 7. The next external bus cycle may start here. READY waitstate order to be safely synchronized. This is guaranteed, if READY is removed in response 37 ST10C167 MUX/Tristate 59/65 ...

Page 60

... HOLD HLDA BREQ CSx (On P6.x) Other Signals Notes 1. The ST10C167 will complete the currently running bus cycle before granting bus access. 2. This is the first possibility for BREQ to become active. 3. The CS outputs will be resistive high (pullup) after 60/65 Max. CPU Clock = 25MHz Min. Max. ...

Page 61

... Notes 1. This is the last opportunity for BREQ to trigger the indicated regain-sequence.Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be deactivated without the ST10C167 requesting the bus. 2. The next ST10C167 driven bus cycle may start here. ...

Page 62

... ST10C167 XX - ELECTRICAL CHARACTERISTICS (continued) The formula for SSC Clock Cycle time Where <SSCBR> represents the content of the SSC Baud rate register, taken as unsigned 16-bit integer. Figure 25 : SSC master timing t 300 1) SCLK t 305 MTSR 1st Out Bit t t 307 308 MRST 1st ...

Page 63

... Idle clock line is low, leading clock edge is low-to-high transition (SSCPO = 0b). 2. The bit timing is repeated for all bits to be transmitted or received TCL * (<SSCBR> 310 311 312 t t 314 313 315 316 315 2nd Out Bit t 317 2nd.In Bit Last.In Bit ST10C167 Last Out Bit t 318 63/65 ...

Page 64

... D 30.95 D1 27. 30.95 E1 27. Note 1. Package dimensions are in mm. The dimensions quoted in inches are rounded. XXII - ORDERING INFORMATION Salestype 1 ST10C167-Q3/XX 1 ST10C167-Q6/XX Note XX : ROM code identification characters 64/65 e 109 0,10 mm .004 inch SEATING PLANE 108 Typical Maximum Minimum 4.07 0.010 3.42 3.67 0.125 ...

Page 65

... The ST logo is a registered trademark of STMicroelectronics 1999 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st .com ST10C167 65/65 ...

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