bt865a Conexant Systems, Inc., bt865a Datasheet
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... Bt864A/Bt865A YCrCb to NTSC/PAL Digital Video Encoder Data Sheet 100138C February 2003 ...
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... Ordering Information Model Number Bt864AKRF YCrCb to NTSC/PAL Digital Video Encoder without Macrovision Bt865AKRF YCrCb to NTSC/PAL Digital Video Encoder with Macrovision Revision History Revision © 2003, Conexant Systems, Inc. All Rights Reserved. Information in this document is provided in connection with Conexant Systems, Inc. (“Conexant”) products. These materials are provided by Conexant as a service to its customers and may be used for informational purposes only ...
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... NTSC-M (N. America, Taiwan, Japan), PAL-B,D,G,H,I (Europe, Asia), PAL–M (Brazil), PAL-N (Uruguay, Paraguay) and PAL–Nc (Argentina). The Bt864A and Bt865A are functionally identical, with the exception that Bt865A can output the Macrovision level 7 anticopy algorithm. Horizontal sync (HSYNC*) and vertical sync (VSYNC*) may be configured as inputs (slave mode) or outputs (master mode) ...
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Conexant 100138C 02/17/03 ...
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Contents Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Copy Generation Management System (CGMS) Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28 1.11 Anticopy Process (Bt865A Only 1-29 1.12 Internal Color Bars 1-29 1 ...
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... Figure 1-18. DAC Sinx/x Response (Passband 1-24 Figure 1-19. Teletext Timing for Tb864A/Bt865A Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26 Figure 1-20. PQ Ratio Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27 Figure 1-21 ...
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... Conexant Bt864A/Bt865A Data Sheet 100138C 02/17/03 ...
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Tables Table 1-1. Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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... Conexant Bt864A/Bt865A Data Sheet 100138C 02/17/03 ...
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... I 14 100138C 02/17/03 Figure 1-1 illustrates the Bt864A/Bt865A pinout diagram, and Description 2x pixel clock input (TTL compatible). Reset control input (TTL compatible). A logical zero disables and resets video timing (horizontal, vertical, subcarrier counters to the start of VSYNC of first field) and resets the I2C interface (but does not reset I2C registers). RESET* must be a logical one for normal operation ...
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... Analog power. Refer to PC Board Considerations section of this document. Digital power. Refer to the PC Board Considerations section of this document. Analog ground. Refer to the PC Board Considerations section of this document. Digital ground. Refer to the PC Board Considerations section of this document. Conexant Bt864A/Bt865A Data Sheet 100138C 02/17/03 ...
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... Bt864A/Bt865A Data Sheet Figure 1-1. Bt864A/Bt865A Pinout Diagram FS ADJUST VBIAS VREF VAA COMP AGND AGND CVBS/B AGND CVBS/G AGND C/R Y/CVBS 100138C 02/17/ Conexant Circuit Description SLEEP TTXREQ VDD GND P[7] P[6] P[5] P[4] P[3] P[2] P[1] P[0] TTXDAT ...
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... Circuit Description Figure 1-2. Detailed Block Diagram 1-4 Conexant Bt864A/Bt865A Data Sheet 100138_003 100138C 02/17/03 ...
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... Bt864A/Bt865A Data Sheet 1.2 Clock TIming A clock signal with a frequency twice the pixel sampling rate must be present at the CLK pin. The device generates an internal pixel CLOCK that in slave mode is synchronized to the HSYNC* pin. This signal is used to increment the horizontal pixel and vertical line counters and to register the pixel (P[7:0], Y[7:0], TTXDAT, RESET*, BLANK*, SLAVE, HSYNC*, and VSYNC*) inputs ...
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... HSYNC* to analog sync out is 40 clocks if SYNCDLY = 0, and 41 clocks if SYNCDLY = 1. In the default mode, the delay from internal horizontal pixel counter reset to the falling edge of HSYNC clocks. 1-6 Figure 1-3). HSYNCF and HSYNCR cannot Table 1-2. If the internal pixel counter resets before the Conexant Bt864A/Bt865A Data Sheet 100138C 02/17/03 ...
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... Bt864A/Bt865A Data Sheet Figure 1-3. HSYNC* Timing in Master Mode Reset ( Internal Pixel Clock/Counter Pixel Count Internal Horizontal Reset Default (2) HSYNC* (1) Horizontal Sync Pipeline Delay Analog Output Video Waveform GENERAL NOTE: Waveforms not to scale. FOOTNOTE: (1) One clock delay (1/2 pixel) of HSYNC* FALLING EDGE, using register SYNCDLY. ...
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... Color burst is disabled on appropriate scan lines. Serration and equalization pulses are generated on appropriate scan lines. In addition, rise and fall times of sync, closed- caption data transitions, and the burst envelope are internally controlled. through show the timing characteristics for various Bt864A/Bt865A modes of operation. Figure 1-4. Interlaced 525-Line (TSC) Video Timing ...
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... Bt864A/Bt865A Data Sheet Figure 1-5. Interlaced 525-Line (PAL-M) Video Timing Analog FIELD 1 523 524 525 1 2 Analog FIELD 2 261 262 263 264 265 Analog FIELD 3 523 524 525 1 2 Analog FIELD 4 261 262 263 264 265 Burst Phase = Reference Phase = 135˚ relative to U PAL Switch = 0, +V Component Burst Phase = Reference Phase + 90˚ ...
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... Analog FIELD Analog FIELD 4 313 314 315 316 317 318 FIELD One FIELD Two FIELD Three FIELD Four Conexant Bt864A/Bt865A Data Sheet VSYNC 319 320 336 337 319 320 336 337 100138_007 100138C 02/17/03 ...
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... Bt864A/Bt865A Data Sheet Figure 1-7. Interlaced 625-Line (PAL- Nc) Video Timing 620 621 622 623 624 625 308 309 310 311 312 620 621 622 623 624 625 308 309 310 311 312 Burst Blanking Intervals Burst Phase = Reference Phase = 135˚ relative to U PAL Switch = 0, +V Component Burst Phase = Reference Phase + 90˚ ...
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... Analog FIELD Analog FIELD 4 313 314 315 316 317 318 FIELD One FIELD Two FIELD Three FIELD Four Conexant Bt864A/Bt865A Data Sheet VSYNC 319 320 336 337 319 320 336 337 100138_009 100138C 02/17/03 ...
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... Bt864A/Bt865A Data Sheet Figure 1-9. Interlaced 625-Line (PAL-N) Video Timing 620 621 622 623 624 625 308 309 310 311 312 620 621 622 623 624 625 308 309 310 311 312 Burst Blanking Intervals Burst Phase = Reference Phase = 135˚ relative to U PAL Switch = 0, +V Component Burst Phase = Reference Phase + 90˚ ...
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... Figure 1-12. Noninterlaced 312-Line (PAL- 308 309 310 311 312 GENERAL NOTE: EVBI = 0. 1-14 RESET* 262 VSYNC* RESET Video Timing c RESET Conexant Bt864A/Bt865A Data Sheet VSYNC 100138_011 100138_012 VSYNC 100138_013 100138C 02/17/03 ...
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... A software reset will occur immediately after writing register SRESET. This will reset all software-programmable register bits to zero. On power-up, the Bt864A/Bt865A will automatically perform a timing and software reset. The power-up state has the following configuration: interlaced, NTSC CCIR601 black burst (no active video), and zero chroma scaling. Setting register EACTIVE will enable active video ...
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... Start of Burst Burst Pulse Width µ HCNT s HCNT ms HCNT 63 4. 4. 4. 4. 4. 4. 4. 4.68 83 5.63 37 Conexant Bt864A/Bt865A Data Sheet (1) Back Porch Front Porch µ µ s HCNT ms HCNT s 2.52 127 9.41 20 1.48 2.52 127 9.41 20 1.48 2.53 115 9.37 18 1.47 2.53 115 9.37 18 1.47 2.22 142 10.52 20 1.48 2.52 142 10.52 20 1.48 2.24 155 10.51 22 1.49 2.51 155 10. ...
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... Bt864A/Bt865A Data Sheet 1.5.3 Master Mode Horizontal sync (HSYNC*) and vertical sync (VSYNC*) are generated from internal timing and from optional software bits. HSYNC* and VSYNC* are output following the rising edge of CLK. The HSYNC* output may be configured to have standard video timing (4.7 µs wide, asserted at start of a line default after RESET cycle may be programmed to specify the start of HSYNC* (10-bit value) and the end of HSYNC* (10-bit value) ...
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... This kills burst as well, providing luminance only signals on the CVBS outputs and a static blank level on the C/R output (RGBOUT = 0). 1-18 Table 1-3 takes precedence over the BLANK* input. and 1-16. For the RGB outputs, the scaled YUV is color space converted Conexant Bt864A/Bt865A Data Sheet Figure 1-4 through . Figure 1-13 and 1-14 100138C ...
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... Bt864A/Bt865A Data Sheet Figure 1-13. Three-Stage Chrominance Filter 5 0 –5 –10 –15 –20 –25 –30 –35 –40 –45 0 Figure 1-14. Three-Stage Chrominance Filter (Passband) 0.5 0 –0.5 –1 –1.5 –2 –2.5 –3 0 0.2 100138C 02/17/ Frequency (MHz) CLK = 27 MHz 0.4 0.6 0.8 1 1.2 1.4 1.6 Frequency (MHz) CLK = 27 MHz Conexant Circuit Description ...
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... Figure 1-15. Luminance 2X Upsampling Filter Response 0 –10 –20 –30 –40 –50 –60 0 Figure 1-16. Luminance 2X Upsampling Filter Response (Passband) 0.5 0 –0.5 –1 –1.5 –2 –2.5 – Frequency (MHz) CLK = 27 MHz Frequency (MHz) CLK = 27 MHz Conexant Bt864A/Bt865A Data Sheet 12 100138_016 12 100138_017 100138C 02/17/03 ...
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... Noninterlaced Operation When the Bt864A/Bt865A is programmed for noninterlaced master mode, the Bt864A/Bt865A always displays FIELD 1, meaning that the falling edges of HSYNC* and VSYNC* will be output coincidentally. FIELD will be held low if FIELDI = 0. Additionally offset will be subtracted from the color subcarrier frequency while in NTSC mode so that the color subcarrier phase will be inverted from field to field ...
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... Register states are preserved, but other chip functionality (including I This mode should be set when the Bt864A/Bt865A may be subjected to clock and data frequencies outside its functional range. In DACOFF power-down mode, (DACOFF register is set to 1) all DACs are disabled and analog current is reduced to approximately 0 mA ...
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... Bt864A/Bt865A Data Sheet 1.7.2 DAC Coding For all video formats, the input luma and chroma values are scaled internally such that, after sync and setup (if enabled) are added, the output from sync to 100% white (for CVBS/Y outputs) is approximately 1. addition, the chroma is boosted to compensate for the sinx/x rolloff due to the DAC ...
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... Closed Captioning The Bt864A/Bt865A encodes NTSC/PAL–M closed captioning on scan line 21 and NTSC/PAL–M extended data services on scan line 284. Four 8-bit registers (CCF1B1, CCF1B2, CCF2B1, and CCF2B2) provide the data while bits ECCF1and ECCF2 enable display of the data. A logical zero corresponds to the blanking level of 0 IRE, while a logical one corresponds to 50 IRE above the blanking level. Closed captioning for PAL– ...
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... Teletext encoding is accomplished via a two-wire interface, TTXDAT and TTXREQ, and internal registers that are programmed through the I encoding in the Bt864A/Bt865A conforms to Teletext B for 625/50 television systems. See “Recommendation 653-1 Teletext Systems” for further information about the standard. Teletext should be disabled for 525-line television systems. ...
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... Circuit Description Figure 1-19. Teletext Timing for Tb864A/Bt865A Encoder TTXREQ TTXDAT (6) CVBS CVBS/G Y/CVBS Internal Horizontal Reset Internal Clock (CLK) (9) Counter GENERAL NOTE: 1. TXE is enabled and video line is a valid teletext line. See "teletext" on page 1-26. FOOTNOTE: (1) Placement of rising edge of TTXREQ is definable using register TXHS[10:0]. ...
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... Bit number: Duration in CLKs: 1.9.3 Teletext Clock Generation Figure 1-20 shifting out the teletext data serially to the Bt864A/Bt865A. The diagram is for illustrative purposes only. The actual implementation is left to the user. Figure 1-20. PQ Ratio Counter Table 1-6. Teletext Clock P and Q Values ...
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... TXRM = 1. In this mode, this teletext clock would only be output on active teletext lines and each line would have exactly 360 clocks to be used to synchronize the teletext data to the Bt864A/Bt865A. The rising edge of clock could be used to latch the data on the output of the device providing the teletext data. The falling of the clock indicates that the Bt864A/Bt865A has received the teletext data ...
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... The anticopy process is licensed for noncommercial, home use only. Reverse engineering or disassembly is prohibited. Conexant cannot ship Bt865A encoders to any customer until that customer has been licensed by Macrovision. Contact Macrovision Corporation to facilitate this license agreement. Parties who have obtained a Macrovision license may receive the Bt865A Macrovision Supplement by contacting Conexant ...
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... This DAC can also provide Green for SCART/ Conexant Bt864A/Bt865A Data Sheet Table 1-7). If the SLEEP pin is high Pin Function Std Mode RGB Out Mode CVBS B CVBS CVBS Tables 1-8 and 1-9). This DAC can Tables 1-10 and 1-11) ...
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... Bt864A/Bt865A Data Sheet Figure 1-22. Y (Luminance) Video Output Waveform SETUPDIS = 26.68 1.000 100 IRE 9.07 0.340 7.5 IRE 7.60 0.285 40 IRE 0.00 0.000 Ω GENERAL NOTE: Typical with 37.5 load, nominal RSET. SMPTE 170 M levels are assumed. 100% saturation color bars (100/7.5/100/7.5) are shown. Table 1-8. Y (Luminance) Video Output Truth Table SETUPDIS = 0 ...
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... FOOTNOTE: (1) BLANK occurs by external BLANK* pin or internally generated BLANK. 1-32 800 736 634 570 470 406 304 DAC Data Sync Interval 800 0 240 0 240 Conexant Bt864A/Bt865A Data Sheet White Level Black/Blank Level Sync Level 100138_024 (1) BLANK 100138C 02/17/03 ...
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... Bt864A/Bt865A Data Sheet Figure 1-24. C (Chrominance) Video Output Waveform SETUPDIS = 28.21 1.058 20.88 0.783 17.07 0.640 13.27 0.498 5.93 0.222 GENERAL NOTE: Typical with 37.5 Ω load, nominal RSET, and chroma on. SMPTE 170 M levels are assumed. 100% saturation color bars (100/7.5/100/7.5) are shown. Table 1-10. C (Chrominance) Video Output Truth Table SETUPDIS = 0 ...
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... Bracketed values indicate expected values when using the internal color bars (100/0/75/0). FOOTNOTE: (1) BLANK occurs by external BLANK* pin or internally generated BLANK. 1-34 Color Burst (10 Cycles) DAC Data Sync Interval 877 [785] x 635 [635] x 512 [512] x 389 [389] x 147 [239] x Conexant Bt864A/Bt865A Data Sheet Blank Level 100138_026 (1) BLANK 100138C 02/17/03 ...
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... Bt864A/Bt865A Data Sheet Figure 1-26. CVBS (Composite) Video Output Waveform SETUPDIS = 32.55 1.221 34 IRE 26.68 1.000 100 IRE 11.41 0.423 9.07 0.340 20 IRE 7.60 0.285 20 IRE 3.80 0.143 40 IRE 3.20 0.120 0.00 0.000 GENERAL NOTE: Typical with 37.5 Ω load, nominal RSET, clipping off, and chroma on. SMPTE 170 M levels are assumed. 100% saturation color bars (100/7 ...
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... Color Burst 406 (10 Cycles) DAC Data Sync Interval 998 [929] 0 800 [800] 0 363 [363] 0 240 [240] 0 240 [240] 0 117 [117 [110 [0] 1 Conexant Bt864A/Bt865A Data Sheet White Level 304 Black/Blank Level Sync Level 100138_028 (1) BLANK 100138C 02/17/03 ...
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... Bt864A/Bt865A Data Sheet Table 1-14. RGB Output Table (RGBOUT = 1) SETUPDIS = 1 Description Iout (mA) White 18.68 Black 0 Blank 0 Iout typical with 37.5 Ω load, nominal RSET. GENERAL NOTE: FOOTNOTE: (1) BLANK occurs by external BLANK* pin or internally generated BLANK 100138C 02/17/03 SETUPDIS = 0 DAC Data Iout (mA) DAC Data 560 18.68 560 0 1 ...
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... Circuit Description 1-38 Conexant Bt864A/Bt865A Data Sheet 100138C 02/17/03 ...
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... ID[2:0] 1 ID[2:0] The ID[2:0] bits indicate the part number returned from the Bt864A returned from the Bt865A. The GENERAL NOTE: version number is indicated by bits VERSION[4:0]. For this revision, VERSION[4:0] = 0x11. The CCSTAT[2] bit is high if closed-caption data has been written for the even field low immediately after the clock run-in on line 284 or 335. The CCSTAT[1] bit is high if closed-caption data has been written for the odd field ...
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... Must be zero for normal operation. This is the default software reset state. 2 (2) Reserved WSDAT[1:4] TXHE[10:8] TXRM TXE TXEF2[8] (2) ECCGATE Reserved DACOFF SYNCDIS ADJHSYNC HSYNCF[9:8] VIDFORM[3:0] DCHROMA ECBAR SCRESET Conexant Bt864A/Bt865A Data Sheet TXHS[10:8] TXBF2[8] TXEF1[8] TXBF1[8] YC16 CBSWAP PORCH HSYNCR[9:8] NONINTL SQUARE EVBI EACTIVE ECLIP PAL-N 100138C 02/17/03 ...
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... Bt864A/Bt865A Data Sheet 2.4 Programming Detail EWSF1 0 = Disable CGMS encoding in field Enable CGMS encoding in field 1 (line 20). EWSF2 0 = Disable CGMS encoding in field Enable CGMS encoding in field 2 (line 283) WSDAT [1:20] CGMS data. SRESET When set to logical one, this will reset all registers, including itself, to logical zero. ...
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... Setup off. The 7.5 IRE setup is disabled. VIDFORM[3:0] Configures the device for various worldwide video formats Bit 2-4 µ s. Format Typical Market NTSC normal USA/Japan 0 0 PAL-M normal Brazil 0 1 PAL-BDGHIN W. Europe 0 1 PAL-Nc Argentina Conexant Bt864A/Bt865A Data Sheet 100138C 02/17/03 ...
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... Bt864A/Bt865A Data Sheet NONINTL 0 = Interlaced operation Noninterlaced operation. SQUARE 0 = CCIR601 operation Square pixel operation. ESTATUS 0 = The I2C read-back information contains the version number The I2C read-back information contains closed-captioning status and field number. RGBO 0 = Normal operation Enable RGB outputs. The RGBOUT pin is logically ORed with the RGBO register bit. ...
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... Internal Registers 2-6 Conexant Bt864A/Bt865A Data Sheet 100138C 02/17/03 ...
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... Component Placement Components should be placed as close as possible to the associated pin. Whenever possible, components should be placed so traces can be connected point to point. The optimum layout enables the Bt864A/Bt865A to be located as close as possible to the power supply connector and the video output connector. 3.2 Power and Ground Planes Separate digital and analog power planes are recommended ...
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... Schottky Diodes RLOAD 1% Metal Film Resistor The vendor numbers above are listed only as a guide. Substitution of devices with similar characteristics will not GENERAL NOTE: affect the performance of the Bt864A/Bt865A. FOOTNOTE: Ω (1) . Conductance combined with the load equals that of a 37.5 Ω resistor. ...
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... Bt864A/Bt865A Data Sheet Figure 3-2. Example Power Plane Layout 3.3 Decoupling 3.3.1 Device Decoupling For optimum performance, all capacitors should be located as close as possible to the device, and the shortest possible leads (consistent with reliable operation) should be used to reduce the lead inductance. Chip capacitors are recommended for minimum lead inductance ...
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... Signal Interconnect 3.4.1 Digital Signal Interconnect The digital inputs to the Bt864A/Bt865A should be isolated as much as possible from the analog outputs and other analog circuitry. Also, these input signals should not overlay the analog power plane or analog output signals. Most of the noise on the analog outputs will be caused by excessive edge rates (less than 3 ns), overshoot, undershoot, and ringing on the digital inputs ...
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... For maximum performance, the analog video output impedance, cable impedance, and load impedance should be the same. The load resistor connection between the video outputs and AGND should be as close as possible to the Bt864A/Bt865A to minimize reflections. Unused DAC outputs should be connected to AGND unless the power-down feature is being utilized ...
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... In some systems, there are signal lines for controlling motors, LEDs, and thermal heads. When a large current flows through these traces problematic noise can result from the phenomenon of mutual inductance (See Figure 3-3. Example of Mutual Inductance 3-6 4-3. Figure Large Current M CLK GND Conexant Bt864A/Bt865A Data Sheet 3-3). 100138_031 100138C 02/17/03 ...
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... RESET* input pin and the digital ground pins (GND) for decoupling purposes. All of Bt864A/Bt865A’s programmable register bits can be reset through software (i.e., setting register bit SRESET= 1). Furthermore, both the Bt864A/Bt865A’s registers and timing can be reset by a low pulse of at least 0.05 µs (>1 complete period of CLK) input directly to RESET*. If noise, having a pulse width close to 0.05 µ ...
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... EMI control after termination should have less than 5 Ω impedance below 5 MHz to minimize additional losses. The capacitor to ground at the Bt864A/Bt865A output pin is compensated for the parasitic capacitance of the chip plus any protection diodes and lumped circuit traces (about 22 pF+5 pF/diode). ...
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... Bt864A/Bt865A Data Sheet clock can generate significant energy at the aural carrier frequency. In the case of hard-edged, unblended characters having a font cell size which is a multiple of three pixels, harmonic energy at the aural carrier frequency may be only 15 dB below the maximum video level, or roughly equal to the power of the sound subcarrier in the RF spectrum ...
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... Bit 8 of the address byte is the read/write bit (high = read from addressed device, low = write to the addressed device) so, for the Bt864A/Bt865A, the address is only considered valid if the R/W bit is low. Data bytes are always acknowledged during the ninth clock pulse by the addressed device ...
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Parametric Information 4.1 DC Electrical Parameters Table 4-1. Recommended Operating Conditions Parameter Symbol Power Supply (VAA and VDD) 3.3V Ambient Operating Temperature DAC Output Load Nominal RSET RSET Table 4-2. Absolute Maximum Ratings Parameter VAA and VDD (measured to ...
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... VIH 2.0 VIL GND –0.5 IIH IIL CIN 7 VIH 0.7 x VDD VIL GND –0.5 VIH 2.4 VIL GND –0.5 VOH 2.4 VOL IOZ CDOUT 10 Conexant Bt864A/Bt865A Data Sheet Max Units 10 Bits VDD + 0.5 V 0.8 V µ µ – VDD + 0.5 V 0.3 x VDD V VDD + 0.5 V ...
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... Bt864A/Bt865A Data Sheet 4.2 AC Electrical Parameters Table 4-4. AC Characteristics (VDD = 5 V, VAA = Parameter (3) Hue Accuracy (3) Color Amplitude Accuracy (4) Chroma AM/PM Noise (3) Differential Gain (3) Differential Phase SNR (unweighted 100 IRE Y Ramp Tilt Correct) RMS (5 MHz Bandwidth) Peak Periodic (4) 100 IRE Multiburst (4.0 MHz Packet) Gain/frequency (4 ...
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... Control pins are defined as: P[7:0], Y[7:0],BLANK*, HSYNC*, VSYNC*, FIELD, TTXREQ, TTXDAT. (6) All digital inputs at GND or VDD. 4-4 EIA/TIA CCIR Symbol Min 250C Ref 567 = 75 pF. As the above parameters are Conexant Bt864A/Bt865A Data Sheet Typ Max Units 52 CLK periods 52 CLK periods 180 ...
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... Bt864A/Bt865A Data Sheet Figure 4-1. YCrCb Video Input and Output Timing CLK P[7:0], Y[7:0] 16-Bit Mode, BLANK*, HSYNC*, VSYNC* P[7:0] 8-Bit Mode, TTXDAT TTXREQ HSYNC*, VSYNC* FIELD (Output) CVBS/B, CVBS/G, Y/CVBS, C/R 100138C 02/17/ 2 Conexant Parametric Information 2.4 .8 Pipeline 100138_034 4-5 ...
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... Figure 4-2. 52-Pin Metric Quad Flatpack (MQFP TOP VIEW SIDE VIEW DETAIL A 4 See Detail A BOTTOM VIEW All Dimensions in Dim. Min. A ---- A1 0.102 A2 1.95 D 17.05 D1 13. 17.05 E1 13. 0. 1.60 REF. b Conexant Bt864A/Bt865A Data Sheet Millimeters Nom. Max. ---- 2.45 ---- ---- 2.00 2.05 17.20 17.35 14.00 14.05 12.00 REF. 17.20 17.35 14.00 14.05 12.00 REF. 0.80 0.90 1.00 BSC. 0.35 REF. 100138_035 100138C 02/17/03 ...
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General Information: U.S. and Canada: (800) 854-8099 International: (949) 483-6996 Headquarters – Newport Beach 4311 Jamboree Rd. Newport Beach, CA. 92660-3007 ...