cx82100 Conexant Systems, Inc., cx82100 Datasheet

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cx82100

Manufacturer Part Number
cx82100
Description
Home Network Processor Hnp
Manufacturer
Conexant Systems, Inc.
Datasheet

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Doc. No. 101306C
April 18, 2002
CX82100
CX82100
CX82100
CX82100
Dissemination, disclosure, or use of this information is not permitted
Home Network Processor (HNP)
Home Network Processor (HNP)
Data Sheet (Preliminary)
Data Sheet (Preliminary)
Home Network Processor (HNP)
Home Network Processor (HNP)
Data Sheet (Preliminary)
Data Sheet (Preliminary)
without the written permission of Conexant Systems, Inc.
Conexant Confidential Information
Conexant Proprietary Information

cx82100 Summary of contents

Page 1

... CX82100 CX82100 CX82100 CX82100 Home Network Processor (HNP) Home Network Processor (HNP) Home Network Processor (HNP) Home Network Processor (HNP) Data Sheet (Preliminary) Data Sheet (Preliminary) Data Sheet (Preliminary) Data Sheet (Preliminary) Conexant Confidential Information Dissemination, disclosure, or use of this information is not permitted without the written permission of Conexant Systems, Inc ...

Page 2

... CX82100 Home Network Processor Data Sheet Revision Record Revision © 2001, 2002 Conexant Systems, Inc. All Rights Reserved. Information in this document is provided in connection with Conexant Systems, Inc. (“Conexant”) products. These materials are provided by Conexant as a service to its customers and may be used for informational purposes only. Conexant assumes no responsibility for errors or omissions in these materials ...

Page 3

... CX82100 Home Network Processor Data Sheet Contents Revision History .......................................................................................................................................... xiv 1 Introduction ......................................................................................................................................... 1-1 1.1 Scope..........................................................................................................................................................................1-2 1.2 Features ......................................................................................................................................................................1-2 1.3 General Hardware Overview.........................................................................................................................................1-3 1.3.1 Advanced Microcontroller Bus Architecture .................................................................................................1-6 1.3.2 ARM940T Processor ...................................................................................................................................1-6 1.3.3 ASB Decoder ...............................................................................................................................................1-6 1.3.4 ASB Arbiter..................................................................................................................................................1-7 1.3.5 ASB Masters................................................................................................................................................1-7 ARM940T Master.................................................................................................................................1-7 DMAC Master ......................................................................................................................................1-7 Host Interface Master ..........................................................................................................................1-7 1.3.6 ASB Slaves ..................................................................................................................................................1-8 ARM940T Slave ...................................................................................................................................1-8 External Memory Controller Slave........................................................................................................1-8 ASB-to-APB Bridge/DMAC ...

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... CX82100 Home Network Processor Data Sheet 2 CX82100 HNP Hardware Interface ....................................................................................................... 2-1 2.1 CX82100 HNP Hardware Interface Signals ..................................................................................................................2-1 2.1.1 CX82100-11/-12/-51/-52 Signal Interface and Pin Assignments ..................................................................2-1 2.1.2 CX82100-41/-42 Signal Interface and Pin Assignments...............................................................................2-1 2.1.3 CX82100 HNP Signal Definitions .................................................................................................................2-1 2.2 CX82100 HNP Electrical and Environmental Specifications........................................................................................2-17 2.2.1 DC Electrical Characteristics ......................................................................................................................2-17 2.2.2 Operating Conditions, Absolute Maximum Ratings, and Power Consumption............................................2-18 2 ...

Page 5

... Host Master Mode Write Control Register 1 (HST_WRITE_CNTL1: 0x002D0018) .....................................5-15 5.3.8 Host Master Mode Write Control Register 2 (HST_WRITE_CNTL2: 0x002D001C).....................................5-15 5.3.9 Host Master Mode Peripheral Size (MSTR_INTF_WIDTH: 0x002D0020) ...................................................5-15 5.3.10 Host Master Mode Peripheral Handshake (MSTR_HANDSHAKE: 0x002D0024) (CX82100-41/-42) ...........5-16 5.3.11 Host Master Mode DMA Source Address (HDMA_SRC_ADDR: 0x002D0028)...........................................5-16 5.3.12 Host Master Mode DMA Destination Address (HDMA_DST_ADDR: 0x002D002C) ....................................5-16 5.3.13 Host Master Mode DMA Byte Count (HDMA_BCNT: 0x002D0030) ...

Page 6

... CX82100 Home Network Processor Data Sheet 7 Ethernet Media Access Control Interface Description .......................................................................... 7-1 7.1 MAC Frame Format .....................................................................................................................................................7-2 7.2 Parameterized Values Used in Implementation ............................................................................................................7-3 7.3 EMAC Functional Features ...........................................................................................................................................7-4 7.4 EMAC Architecture ......................................................................................................................................................7-6 7.5 Media Independent Interface (MII) ..............................................................................................................................7-7 7.6 EMAC Interrupts..........................................................................................................................................................7-8 7.7 TMAC Architecture ......................................................................................................................................................7-9 7.7.1 Transmit Frame Structure............................................................................................................................7-9 7.7.2 Transmit Descriptor...................................................................................................................................7-11 7.7.3 Transmit Status (TSTAT) ...........................................................................................................................7-12 7 ...

Page 7

... CX82100 Home Network Processor Data Sheet 8.3 UDC Core ....................................................................................................................................................................8-6 8.3.1 Endpoint Buffer Format................................................................................................................................8-6 8.3.2 Example of Endpoint Buffer Encoding..........................................................................................................8-7 8.3.3 Loading of the EndPtBuf Configurations ......................................................................................................8-8 8.3.4 USB Command Handling .............................................................................................................................8-9 8.4 USB DMA Interface ...................................................................................................................................................8-10 8.4.1 DMA Receive Channel................................................................................................................................8-10 8.4.2 DMA Transmit Channel..............................................................................................................................8-12 8.5 Interrupt Endpoint .....................................................................................................................................................8-14 8.6 Summary of the Endpoints ........................................................................................................................................8-14 8.7 USB Register Memory Map .......................................................................................................................................8-15 8 ...

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... CX82100 Home Network Processor Data Sheet 9 General Purpose Input/Output Interface Description............................................................................ 9-1 9.1 GPIO Pin Description...................................................................................................................................................9-1 9.2 GPIO Register Memory Map........................................................................................................................................9-2 9.3 GPIO Registers............................................................................................................................................................9-3 9.3.1 GPIO Option Register for GPIO[39:37; 32] (GPIO_OPT: 0x003500B0) ........................................................9-3 9.3.2 GPIO Output Enable Register 1 for GPIO[15:14; 8:5] (GPIO_OE1: 0x003500B4) .........................................9-4 9.3.3 GPIO Output Enable Register 2 for GPIO[31; 27:16] (GPIO_OE2: 0x003500B8) ..........................................9-4 9.3.4 GPIO Output Enable Register 3 for GPIO[39:37 ...

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... CX82100 Home Network Processor Data Sheet 12.5 Timer Registers.........................................................................................................................................................12-3 12.5.1 Timer 1 Counter Register (TM_Cnt1: 0x00350020) ...................................................................................12-3 12.5.2 Timer 2 Counter Register (TM_Cnt2: 0x00350024) ...................................................................................12-3 12.5.3 Timer 3 Counter Register (TM_Cnt3: 0x00350028) ...................................................................................12-4 12.5.4 Timer 4 Counter Register (TM_Cnt4: 0x0035002C) ...................................................................................12-4 12.5.5 Timer 1 Limit Register (TM_Lmt1: 0x00350030).......................................................................................12-4 12.5.6 Timer 2 Limit Register (TM_Lmt2: 0x00350034).......................................................................................12-4 12.5.7 Timer 3 Limit Register (TM_Lmt3: 0x00350038).......................................................................................12-5 12 ...

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... CX82100 Home Network Processor Data Sheet Figures Figure 1-1. CX82100 HNP Major System Interface ..........................................................................................................1-3 Figure 1-2. CX82100 HNP Typical System Interface – Residential Gateway Firewall plus Router Application ...................1-4 Figure 1-3. CX82100 HNP Typical System Interface – Ethernet/HomePNA 2.0 Bridge Application ...................................1-4 Figure 1-4. CX82100 HNP Block Diagram........................................................................................................................1-5 Figure 1-5 ...

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... CX82100 Home Network Processor Data Sheet Figure 8-3. USB Receive Data Flow..................................................................................................................................8-4 Figure 8-4. Example of an USB Device for HNP ...............................................................................................................8-7 Figure 8-5. Loading of the EndPtBuf Configurations ........................................................................................................8-9 Figure 8-6. DMA Channel Supporting USB Receive OUT Endpoints ...............................................................................8-10 Figure 8-7. DMA Channels for USB Transmit IN Endpoints............................................................................................8-12 Figure 9-1. GPIO[x] Interface...........................................................................................................................................9-1 Figure 13-1 ...

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... Table 5-3. Timing for Host Master Mode Read Operation Based on a 100 MHz BCLK (CX82100-11/-12/-51/-52)............5-6 Table 5-4. Timing for Host Master Mode Write Operation Based on a 100 MHz BCLK (CX82100-11/-12/-51/-52) ...........5-7 Table 5-5. Timing for Host Master Mode Read Operation Based on a 100 MHz BCLK (CX82100-41/-42) ......................5-10 Table 5-6 ...

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... Table 13-6. BCLK PLL Generated Clocks Programming Examples .................................................................................13-4 Table 13-7. PLL Register Memory Map .........................................................................................................................13-5 Table 13-8. Desired Frequencies and Programming Parameters....................................................................................13-8 Table 13-9. Clocking Requirements ...............................................................................................................................13-9 Table 14-1. Register Type Definition..............................................................................................................................14-1 Table 14-2. CX82100 Interface Registers Sorted by Supported Function .......................................................................14-2 Table 14-3. CX82100 Interface Registers Sorted by Address.........................................................................................14-6 Conexant Proprietary and Confidential Information 101306C xiii ...

Page 14

... Figure 2-4: Revised pin N13 to VSSO rather than VDDO for CX82100-41/-42. 4. Table 2-2: Revised pin N13 to VSSO rather than VDDO for CX82100-41/-42. 5. Table 2-3: Revised pin N13 to VSSO rather than VDDO for CX82100-41/-42. Table 2-9: Revised GPIO20 to LAN 1 Reset (LAN1_RST#) rather than GPIO5. 6. Table 2-10: Revised GPIO20 to LAN 1 Reset (LAN1_RST#) rather than GPIO5. ...

Page 15

... CX82100-41 supports basic functions and programmable HRDY# polarity for wireless applications (see Section 5.1.6). The CX82100-41 supports the following two signals on the indicated pins (different from the CX82100-11): P13 = HC00 (HCS0#)/GPIO32 and P14 = HC10 (HRDY#) (see Section 2.1.2). Recommended for new designs. ...

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... CX82100 Home Network Processor Data Sheet CX82100-42 supports basic functions, programmable HRDY# polarity for wireless 6. applications and Intoto Firewall software. Same pinout as the CX82100-41. Recommended for new designs. 1.1 Scope This document describes the CX82100 HNP hardware architecture. 1.2 Features • Single-chip, high-performance processor with integrated network interfaces − ...

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... CX82100 Home Network Processor Data Sheet 1.3 General Hardware Overview The major CX82100 HNP internal components (also referred to as blocks or functions) and external interfaces of the CX82100 HNP are illustrated in Figure 1-1. A typical system interface for a Residential Gateway Firewall plus Router application using the CX82100 HNP is illustrated in Figure 1-2. ...

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... CX82100 Home Network Processor Data Sheet Figure 1-2. CX82100 HNP Typical System Interface – Residential Gateway Firewall plus Router Application CX82100 Hom e Netw ork Processor (HNP) ARM940T Processor Random Read-Only Access Mem ory (RAM) External SDRAM Mem ory Control Logic or SRAM Controller ...

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... CX82100 Home Network Processor Data Sheet Figure 1-4. CX82100 HNP Block Diagram IRQ # FIQ # Master/Slave (M /S) Advanced System Bus (ASB) External S S SDRAM/ SRAM RAM EMC (8k x 32) CX82100 HNP Conexant Proprietary and Confidential Information 101306C ARM 940T Processor ARM9TDMI Core Instruction System ...

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... CX82100 Home Network Processor Data Sheet 1.3.1 Advanced Microcontroller Bus Architecture The HNP internal architecture is based on the Advanced Microcontroller Bus Architecture (AMBA) which defines two internal busses, the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB). • The 32-bit ASB is a high performance, burst-mode, pipelined bus, which connects multiple bus masters ...

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... CX82100 Home Network Processor Data Sheet 1.3.4 ASB Arbiter The ASB Arbiter performs arbitration on the ASB to ensure that only one ASB master at a time is allowed to initiate data transfers. No arbitration scheme is enforced, therefore, either 'highest priority' or 'fair' access algorithms may be implemented, depending on the application requirements ...

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... CX82100 Home Network Processor Data Sheet 1.3.6 ASB Slaves ASB slaves respond to read or write operations within a given address-space range. A bus slave signals the success, failure, or waiting of the data transfer back to the active master. The ASB slaves in the HNP ASIC are the ARM940T (test mode only), EMC, ASB-to- APB Bridge/DMAC, internal ROM, and internal SRAM ...

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... CX82100 Home Network Processor Data Sheet 1.3.7 APB Functions The Advanced Peripheral Bus (APB) provides signaling for I/O functions. EMAC Interface Dual Media Independent Interface (MII) or 7-Wire Serial (7-WS) interfaces, controlled by two identical HNP 10/100BaseT Ethernet MAC (EMAC) blocks, optionally connect interchangeably to devices such as an Ethernet transceiver PHY, Conexant CX24611 HomePNA 2 ...

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... Typical Home Networking Architecture Typical home networking architecture for a Residential Gateway Firewall plus Router box with an installed CX82100 HNP-based Ethernet-to-Ethernet interface is illustrated in Figure 1-5. This box allows multiple home PCs to access the Internet through a single point of connection. All the home PCs connect to the in-house RJ-45 wiring using the CX82100 HNP-based Ethernet interface ...

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... CX82100 Home Network Processor Data Sheet Figure 1-5. Example of a Residential Gateway Firewall plus Router Application Hom e PC Residential Gatew ay (RG) Firew all Plus Router using the CX82100 HNP Broadband Access Device Network Server Conexant Proprietary and Confidential Information 101306C Hom e PC ...

Page 26

... CX82100 Home Network Processor Data Sheet Figure 1-6. Example of a HomePNA 2.0 Bridge Application Hom e PC Printer Fax Hom e PNA 2.0 Bridge using the CX82100 HNP Broadband Access Device Network Server Conexant Proprietary and Confidential Information 1-12 Laptop com puter Hom e PC Hom ePNA 2.0 Phone Line Netw ork Hom ePNA 2 ...

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... CX82100 Home Network Processor Data Sheet 1.6 References [1] ARM9TDMI Data Sheet, November, 1997, ARM Limited. [2] ARM940T Data Sheet, November, 1997, ARM Limited. [3] AMBA–Advanced Microcontroller Bus Architecture Specification, April, 1997, ARM Limited. [4] ANSI/IEEE 802.3, Reference Number ISO/IEC 8802-3, Part 3: Carrier Sense Multiple Access with Collision detection (CSMA/CD) Access Method and Physical Layer Specifications, Fifth Edition, 1996-07-29 ...

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... CX82100 Home Network Processor Data Sheet 1.7 Key Words 7-WS or 7WS AFE AMBA APB ARM ASB ASIC CRC DMAC EMAC EMC FIFO GPIO GPSI HomePNA HomePlug ICE LSb LSB MAC MII MSb MSB OSI PHY SOHO STA TIC Conexant Proprietary and Confidential Information ...

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... CX82100 Home Network Processor Data Sheet 1.8 Conventions 1.8.1 Data Lengths qword dword word byte nibble 1.8.2 Register Descriptions Register Type RW* RR RWp Wd Conexant Proprietary and Confidential Information 101306C 64-bits 32-bits 16-bits 8 bits 4 bits Description Read-only Write-only Read/Write Read/Write, but data may not be same as written at a later time ...

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... CX82100 Home Network Processor Data Sheet Conexant Proprietary and Confidential Information 1-16 This page is intentionally blank. 101306C ...

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... Note: 2.1.2 CX82100-41/-42 Signal Interface and Pin Assignments CX82100-41/-42 HNP hardware interface signals are shown in Figure 2-3. CX82100-41/-42 HNP pin signals are shown in Figure 2-4 and are listed in Table 2-2. Note: 2.1.3 CX82100 HNP Signal Definitions CX82100 HNP hardware interface signals are defined in Table 2-3. CX82100 HNP input/output types are described in Table 2-4. ...

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... CX82100 Home Network Processor Data Sheet Figure 2-1. CX82100-11/-12/-51/-52 HNP Hardware Interface Signals G1 COL G2 CRS K8 MDC M8 MDIO G5 RX_CLK H4 RXD0 H3 RXD1 H1 RXD2 MEDIA INDEPENDENT H2 RXD3 INTERFACE 1 (MII 1)/ L7 7-WIRE SERIAL RXDV P8 INTERFACE (7-WS1) RXER E1 TX_CLK F1 TX_EN F2 TXD0 F5 TXD1 F3 TXD2 E4 TXD3 G3 TXER B8 COL J12 ...

Page 33

... CX82100 Home Network Processor Data Sheet Figure 2-2. CX82100-11/-12/-51/-52 HNP Pin Signals-196-Pin FPBGA GPIO18 TST2 GPIO24 GPIO17 GPIO19 TST1 GPIO20 VDDO NC VSSO GPIO21 NC TST3 VDDO NC I2C_DATA (GPIO15) EM1_TXD3 EM1_TX_CLK ...

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... CX82100 Home Network Processor Data Sheet Table 2-1. CX82100-11/-12/-51/-52 HNP Pin Signals – 196-Pin FPBGA Pin Signal Pin A1 GPIO24 D8 A2 GPIO18 D9 A3 GPIO17 D10 A4 TST2 D11 A5 VSSO D12 A6 EM2_MDIO D13 A7 EM2_RXD1 D14 A8 GPIO26 E1 A9 MB0 E2 A10 MA00 E3 A11 MA04 E4 A12 VDDO E5 A13 ...

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... CX82100 Home Network Processor Data Sheet Figure 2-3. CX82100-41/-42 HNP Hardware Interface Signals G1 COL G2 CRS K8 MDC M8 MDIO G5 RX_CLK H4 RXD0 H3 RXD1 H1 RXD2 MEDIA INDEPENDENT H2 RXD3 INTERFACE 1 (MII 1)/ L7 7-WIRE SERIAL RXDV P8 INTERFACE (7-WS1) RXER E1 TX_CLK F1 TX_EN F2 TXD0 F5 TXD1 F3 TXD2 E4 TXD3 G3 TXER B8 COL J12 ...

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... CX82100 Home Network Processor Data Sheet Figure 2-4. CX82100-41/-42 HNP Pin Signals-196-Pin FPBGA GPIO18 TST2 GPIO24 GPIO17 GPIO19 TST1 GPIO20 VDDO NC VSSO GPIO21 NC TST3 VDDO NC I2C_DATA (GPIO15) EM1_TXD3 EM1_TX_CLK ...

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... CX82100 Home Network Processor Data Sheet Table 2-2. CX82100-41/-42 HNP Pin Signals – 196-Pin FPBGA Pin Signal Pin A1 GPIO24 D8 A2 GPIO18 D9 A3 GPIO17 D10 A4 TST2 D11 A5 VSSO D12 A6 EM2_MDIO D13 A7 EM2_RXD1 D14 A8 GPIO26 E1 A9 MB0 E2 A10 MA00 E3 A11 MA04 E4 A12 VDDO E5 A13 ...

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... CX82100 Home Network Processor Data Sheet Table 2-3. CX82100 HNP Pin Signal Definitions Pin Signal Pin No. VDD H7, H8 VDDA G6 VDDO A12, B3, B5, D1, D14, F6, F9, F12, H10, J7, K7, K11, N5, N9, N11, P1 VDDO N13 (CX82100 -11/-12/-51/-52) VGG H6 VSS G7, G8 VSSA H5 A5, B9, B11, VSSO C4, D8, D12, ...

Page 39

... CX82100 Home Network Processor Data Sheet Table 2-3. CX82100 HNP Pin Signal Definitions (Continued) Pin Signal Pin No. USBP D9 USBN E8 USB_PWR_DET C9 (GPIO22) TRST# J4 TCK K2 TMS J6 TDI K1 TDO K3 Test Interface Controller (TIC) [Factory Test Only] TREQA K5 Conexant Proprietary and Confidential Information 101306C I/O I/O Type USB Interface ...

Page 40

... CX82100 Home Network Processor Data Sheet Table 2-3. CX82100 HNP Pin Signal Definitions (Continued) Pin Signal Pin No. EM1_COL G1 EM1_CRS G2 EM1_MDC K8 EM1_MDIO M8 EM1_RX_CLK G5 Conexant Proprietary and Confidential Information 2-10 I/O I/O Type EMAC 1 Interface I Itpd LAN 1 Collision Indication. In full-duplex mode, EM1_COL is ignored. In half-duplex mode, EM1_COL is asserted by the LAN 1 EPHY upon detection of a collision on the medium, and remains asserted while the collision condition persists ...

Page 41

... CX82100 Home Network Processor Data Sheet Table 2-3. CX82100 HNP Pin Signal Definitions (Continued) Pin Signal Pin No. EM1_RXD[3:0] H2, H1, H3, H4 EM1_RXDV L7 EM1_RXER P8 EM1_TX_CLK E1 EM1_TX_EN F1 EM1_TXD[3:0] E4, F3, F5, F2 Conexant Proprietary and Confidential Information 101306C I/O I/O Type LAN 1 Receive Data. For MII interface, EM1_RXD[3:0] are the 4- ...

Page 42

... CX82100 Home Network Processor Data Sheet Table 2-3. CX82100 HNP Pin Signal Definitions (Continued) Pin Signal Pin No. EM1_TXER G3 The EMAC 2 interface is the same as the EMAC 1 interface. Refer to the EMAC1 interface for signal definitions. EM2_COL B8 EM2_CRS J12 EM2_MDC B6 EM2_MDIO A6 EM2_RX_CLK C8 EM2_RXD[3:0] E7, B7, A7, ...

Page 43

... CX82100 Home Network Processor Data Sheet Table 2-3. CX82100 HNP Pin Signal Definitions (Continued) Pin Signal Pin No. HAD[15:0] N7, M9, L8, K9, J9, N10, P10, M10, L9, K10, L10, M11, J10, L11, N12, P12 L3, L1, M2, M1, HAD[29:16] N2, N1, M3, N3, P3, M4, N4, P4, L4, M5 HC[07:01] L5, M6, K6, N6, P6, L6, P7 HC08 (HRD#) ...

Page 44

... CX82100 Home Network Processor Data Sheet Table 2-3. CX82100 HNP Pin Signal Definitions (Continued) Pin Signal Pin No. MA[11:00] B13, C12, A13, B12, D11, C11, F8, A11, C10, D10, B10, A10 MD[15:00] J14, H12, H13, J11, H14, G13, G12, H9, G14, G10, F13, G11, F14, F10, E13, ...

Page 45

... CX82100 Home Network Processor Data Sheet Table 2-3. CX82100 HNP Pin Signal Definitions (Continued) Pin Signal Pin No. MWE# B14 MCKE E12 MCLK E14 Recommended GPIO usage is listed in Table 2-9. GPIO31 C6 GPIO27 G4 GPIO26 A8 GPIO24 A1 GPIO21 C3 GPIO20 B1 GPIO19 B2 GPIO18 A2 GPIO17 A3 GPIO8 D5 GPIO7 E5 GPIO6 D6 GPIO5 E6 TST[3:0] ...

Page 46

... CX82100 Home Network Processor Data Sheet Table 2-4. CX82100 HNP Input/Output Type Descriptions I/O Type It Digital input, +5V tolerant It/Ot4 Digital input, +5V tolerant pF/Digital output, 4 mA, Z INT = 80 Ω Ith Digital input, +5V tolerant, with hysteresis Ithpd Digital input, +5V tolerant, with hysteresis, 75k Ω pull-down Itpd Digital input, +5V tolerant, 75k Ω ...

Page 47

... CX82100 Home Network Processor Data Sheet 2.2 CX82100 HNP Electrical and Environmental Specifications 2.2.1 DC Electrical Characteristics CX82100 HNP DC electrical characteristics are listed in Table 2-5. Table 2-5. CX82100 HNP DC Electrical Characteristics Parameter Input high voltage Input low voltage Input leakage current Input leakage current (with internal pull- ...

Page 48

... CX82100 Home Network Processor Data Sheet 2.2.2 Operating Conditions, Absolute Maximum Ratings, and Power Consumption CX82100 HNP operating conditions are specified in Table 2-6. CX82100 HNP absolute maximum ratings are stated in Table 2-7. CX82100 HNP power consumption is listed in Table 2-8. Table 2-6. CX82100 HNP Operating Conditions Core circuits supply voltage ...

Page 49

... CX82100 Home Network Processor Data Sheet 2.3 Optional GPIO and Host Signal Usage Optional GPIO and host signal usage is listed in Table 2-9. Recommended GPIO signals are described in Table 2-10. Table 2-9. CX82100 HNP Recommended GPIO and Host Signal Use Pin Name Pin FCLKIO/GPIO39 J1 BCLKIO/GPIO38 J5 HAD31 (HCS4#)/GPIO37 ...

Page 50

... CX82100 Home Network Processor Data Sheet Table 2-10. CX82100 HNP Definitions of Recommended GPIO and Host Signals Pin Signal Pin No. LED_READY (GPIO7) E5 LAN1_RST# (GPIO20) B1 LAN2_RST# (GPIO6) D6 Conexant Proprietary and Confidential Information 2-20 I/O I/O Type LED Indicator Interface O Itpu/Ot4 READY Indicator. Active high output indicating the HNP is ready. ...

Page 51

... CX82100 Home Network Processor Data Sheet 2.4 Interface Timing and Waveforms 2.4.1 External Memory Interface (SDRAM) The External Memory Interface provides a PC100-compatible SDRAM interface. Signal interface timing is summarized in Figure 2-5. Note that MCLK is derived from the BCLK PLL output (see Section 12). Accordingly, there is no fixed relationship between the HNP clock input (CLKI pin) and the External Memory Interface signals ...

Page 52

... CX82100 Home Network Processor Data Sheet 2.4.6 Interrupt Timing To be added. 2.4.7 Clock Reset Timing To be added. 2.4.8 Reset Timing To be added. Conexant Proprietary and Confidential Information 2-22 101306C ...

Page 53

... CX82100 Home Network Processor Data Sheet 2.5 Package Dimensions The package dimensions for the 196-pin FPBGA are shown in Figure 2-6. Figure 2-6. Package Dimensions – 196-Pin FPBGA D Top View Side View A2 Conexant Proprietary and Confidential Information 101306C ...

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... CX82100 Home Network Processor Data Sheet Conexant Proprietary and Confidential Information 2-24 This page is intentionally blank. 101306C ...

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... CX82100 Home Network Processor Data Sheet 3 HNP Memory Architecture 3.1 HNP Memory Map The HNP system memory map is shown in Figure 3-1. All internal and external memory and APB peripheral registers are memory-mapped directly to the first 16 MB region of the ASB 32-bit address space. Note that the map shows only the memory range reserved for each ASB slave ...

Page 56

... CX82100 Home Network Processor Data Sheet Figure 3-1. HNP Memory Map 0x00000000 0x0007FFFF 0x00080000 0x000FFFFF 0x00100000 0x0017FFFF 0x00180000 0x001FFFFF 0x00200000 0x002FFFFF 16 MB Space 0x00300000 0x003FFFFF 0x00400000 0x007FFFFF 0x00800000 0x00FFFFFF 0x01000000 0x80000000 0xFFFFFFFF Conexant Proprietary and Confidential Information 3-2 Run-Time Memory Map ARM Vector Table (32 Bytes) ...

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... CX82100 Home Network Processor Data Sheet 3.2 Starting Addresses The starting addresses for mapping ASB and APB slaves are defined in Table 3-1 and Table 3-2, respectively. Table 3-1. Starting Addresses for Mapping ASB Slaves ASB Address: BA[31:0] 0x000XXXXX 0x0018XXXX 0x002XXXXX 0x003XXXXX 0x00400000– 0x007FFFFF 0x00800000 - 0x00FFFFFF 0x80000000 Table 3-2 ...

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... CX82100 Home Network Processor Data Sheet 3.3 Endianness The internal bus architecture supports only Little-Endian mode addressing (see Figure 3-2). Support for Big-Endian mode may occur in a peripheral that handles its data stream or in the host interface which may exchange data with a Big-Endian mode external processor ...

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... CX82100 Home Network Processor Data Sheet Figure 3-3. Boot Procedure Internal ROM boot(GPIO14=1) Power-On-Reset Begin execution of the ROM code. Read signature bytes (first 4 bytes) of EEPROM. Is the signature present? Y Read from EEPROM, Read from internal ROM, Device Descriptor, Device Device Descriptor, Device Config ...

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... CX82100 Home Network Processor Data Sheet Conexant Proprietary and Confidential Information 3-6 This page is intentionally blank. 101306C ...

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... CX82100 Home Network Processor Data Sheet 4 DMAC Interface Description The DMA controller (DMAC) is both an ASB master and an APB master integrated with the ASB-to-APB bridge. Using burst transfers and pipelining the data within the bus bridge interface optimizes ASB efficiency. ...

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... CX82100 Home Network Processor Data Sheet peripheral makes a DMA data transfer request, however, it should not make another until after the current request has been processed (APB read or write left up to the requestor (not the DMAC) to log any overflow or underflow conditions. ...

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... CX82100 Home Network Processor Data Sheet 4.4 DMAC Register Memory Map DMAC registers are identified in Table 4-3. Table 4-3. DMAC Registers Register Label Register Name DMAC_1_Ptr1 DMAC 1 Current Pointer 1 DMAC_2_Ptr1 DMAC 2 Current Pointer 1 DMAC_3_Ptr1 DMAC 3 Current Pointer 1 DMAC_4_Ptr1 DMAC 4 Current Pointer 1 DMAC_5_Ptr1 DMAC 5 Current Pointer 1 ...

Page 64

... CX82100 Home Network Processor Data Sheet 4.5 Control Register Formats 4.5.1 DMAC x Current Pointer 1 (DMAC_{x}_Ptr1) Bit(s) Type Default 31:24 23:2 RW* 22’bx DMAC_{x}_Ptr1 1:0 4.5.2 DMAC x Indirect/Return Pointer 1 (DMAC_{x}_Ptr2) Bit(s) Type Default 31:24 23:2 RW* 22’bx DMAC_{x}_Ptr2 1:0 4.5.3 DMAC x Buffer Size Counter 1 (DMAC_{x}_Cnt1) Bit(s) Type ...

Page 65

... CX82100 Home Network Processor Data Sheet 4.5.5 DMAC x Buffer Size Counter 3 (DMAC_{x}_Cnt3) Bit(s) Type Default 31:11 10:0 RW* 11’bx DMAC_{x}_Cnt3 Conexant Proprietary and Confidential Information 101306C Name Reserved. Saved DMA Buffer Size in No. of qwords. Description 4-5 ...

Page 66

... CX82100 Home Network Processor Data Sheet 4.6 Three Basic Modes of Address Generation 4.6.1 Source or Destination Mode DMAC_{x}_Ptr1 is initialized by the microcontroller to point to the beginning of a dword-aligned source or destination buffer. This pointer advances (by 1 qword) after each transfer request X{x}R. Reading this pointer returns the current qword location to be handled next by the DMAC when it processes the channel request ...

Page 67

... CX82100 Home Network Processor Data Sheet The usage of each register for controlling the operation of the circular buffer is as follows: • DMAC_{x}_Ptr2. Used as a base pointer to a dword-aligned circular buffer and is loaded by the microcontroller (by writing to DMAC_{x}_Ptr1) just once (i.e., this pointer value is fixed) after the buffer has been allocated. This buffer is typically big enough to handle multiple data packets (packet size is 64 bytes for USB) ...

Page 68

... CX82100 Home Network Processor Data Sheet qwords is determined by DMA_{x}_Cnt2. If there are N cluster descriptors then the value 2N should be written to DMA_{x}_Cnt2. The DMAC prefetches the cluster pointers to a two-pointer queue using a source DMA channel. This queue is initialized (filled) automatically as soon as the firmware writes to DMA_{x}_Cnt2 (so CDT must be valid and DMA_{x}_Ptr2 initialized) ...

Page 69

... CX82100 Home Network Processor Data Sheet to be stored at the same cluster location. The limiter, DMA_{X}_Cnt1, is used to prevent the EMAC-RxD channel from overwriting the allocated cluster buffer size. The protocol for this DMA channel is: ARM initializes the CDT. 1. ARM initializes DMA_{X}_Ptr2 with the base pointer to CDT (a copy saved within 2 ...

Page 70

... CX82100 Home Network Processor Data Sheet Figure 4-2. Embedded Tail Linked List Descriptor Example 0x00140248 0x0014024C 0x00140250 0x00140254 0x00140258 0x0014025C 0x00140260 0x00140264 0x00140268 0x0014026C 0x00140470 0x00140474 0x00140478 0x0014047C 0x00140480 0x00140484 0x00140488 0x0014048C Conexant Proprietary and Confidential Information 4-10 4 Bytes Ctl Hdr DMAC_{x}_Ptr2= 0x00140248 ...

Page 71

... CX82100 Home Network Processor Data Sheet The usage of each register for controlling the operation of the Embedded Tail Linked List Descriptor mode is described below. • DMAC_{x}_Ptr1: Loaded with an initial pointer to a dword-aligned source buffer. A copy of the pointer is automatically saved in DMAC_{x}_Ptr2 whenever DMAC_{x}_Ptr1 is loaded with a new pointer ...

Page 72

... CX82100 Home Network Processor Data Sheet Indirect/Table Linked List Descriptor Mode The example shown in Figure 4-3 illustrates the use of the indirect/table linked descriptor mode for four transmit buffers. The DMAC operation is virtually identical to that of the embedded tail linked list descriptor mode except that the next DMA Ptr1 and Cnt1 will be fetched from a pre-programmed pointer/counter table ...

Page 73

... CX82100 Home Network Processor Data Sheet The use of the tail and the indirect/table linked list descriptor modes can be mixed to form a more complicated list. The dynamic switch from one mode to the other is controlled by the pre-programmed value in DMAC_{x}_LMode. Figure 4-4 shows an example for mixing the two modes with five buffers. ...

Page 74

... CX82100 Home Network Processor Data Sheet Conexant Proprietary and Confidential Information 4-14 This page is intentionally blank. 101306C ...

Page 75

... CX82100 Home Network Processor Data Sheet 5 Host Interface Description The Host Interface operates in Master Mode which allows the HNP to access external Flash ROM and an optional slave device. The host interface master mode operates asynchronously and is not referenced to any host clock input or output. ...

Page 76

... CX82100 Home Network Processor Data Sheet Table 5-1. Host Master Mode Signals Pin Signal Host Master Mode Signal HAD[15:0] HD[15:0] HAD[29:16] HA[20:7] HC[07:01] HA[6:0] HC08 (HRD#) HRD# HC09 (HWR#) HWR# HC10 (HRDY#) HRDY# HC00 (HCS0#)/GPIO32* HCS0# HAD31 (HCS4#)/GPIO31* HCS4# Notes These pins default to host functions; they can be reconfigured to GPIO pins. ...

Page 77

... CX82100 Home Network Processor Data Sheet Table 5-2. Chip Select Address Ranges HCS Signal HCS0# (HC00) HCS4# (HAD31) 5.1.2 Flash Memory Interface The master mode host interface addresses Mbit ( 16) of Flash ROM using HA[21:1]. HCS0# is designed specifically to select Flash ROM. Flash ROM can be optionally used for the HNP executable memory instead of internal ROM ...

Page 78

... CX82100 Home Network Processor Data Sheet If internal DMA timer is selected, a value must be written to HDMA_ISOC_TIMER. This value is, in terms of BCLK periods, the time between DMA accesses to the external peripheral. For example, when DMAing data from a peripheral to an internal destination this register value determines the rate data is read from the peripheral. ...

Page 79

... CX82100 Home Network Processor Data Sheet 5.1.5 Host Master Mode Timing (CX82100-11/-12/-51/-52) Host Master Mode Read Operation (Accessing an External Device) The Host Master Mode read timing is illustrated in Figure 5-3 and listed in Table 5-3. HRD# and HWR# signals are used when the appropriate bit of the Host Master • ...

Page 80

... Figure 5-3. Waveforms for Host Master Mode Read Operation (CX82100-11/-12/-51/-52) HA[21:1] HD[15:0] HCS[X]# HRD HR/W # HDS# Tas Table 5-3. Timing for Host Master Mode Read Operation Based on a 100 MHz BCLK (CX82100-11/-12/-51/-52) Symbol Tas Programmable address setup to active read Tpw Programmable read pulse width Tds Required data setup to end of active read Tdh ...

Page 81

... HD[15:0] HCS[X]# HRD HR/W # HDS# Tas Table 5-4. Timing for Host Master Mode Write Operation Based on a 100 MHz BCLK (CX82100-11/-12/-51/-52) Symbol Tas Programmable address setup to active write Tpw Programmable read pulse width Tadh Programmable address and data hold time following active write (address hold time is longer that data hold time so min ...

Page 82

... CX82100 Home Network Processor Data Sheet 5.1.6 Host Master Mode Timing (CX82100-41/-42) Host Master Mode Read Operation (Accessing an External Device) The Host Master Mode read timing is illustrated in Figure 5-5 and listed in Table 5-5. • HRD# and HWR# signals are used when the appropriate bit of the Host Master Mode Transfer Control Register is low ...

Page 83

... CX82100 Home Network Processor Data Sheet HRDY# Description (CX82100-41/-42) HRDY# is used to extend a Host Interface operation. The use of HRDY# can be enabled or disabled by setting or clearing the corresponding HRDY# Handshake Enable bit in the MSTR_HANDSHAKE register (0x002D0024). When HRDY# is enabled, the polarity of HRDY# can be programmed by setting or clearing bit 0 of the MSTR_HANDSHAKE register. • ...

Page 84

... Figure 5-5. Waveforms for Host Master Mode Read Operation (CX82100-41/-42) HA[21:1] HD[15:0] HCS[X]# HRD# HWR# HR/W# HDS# HRDY# Table 5-5. Timing for Host Master Mode Read Operation Based on a 100 MHz BCLK (CX82100-41/-42) Symbol Tas Programmable address setup to active read Tpw Programmable read pulse width Tds Required data setup to end of active read Tdh ...

Page 85

... HCS[X]# HRD# HWR# HR/W# HDS# HRDY# Tas Table 5-6. Timing for Host Master Mode Write Operation Based on a 100 MHz BCLK (CX82100-41/-42) Symbol Tas Programmable address setup to active write Tpw Programmable read pulse width Tadh Programmable address and data hold time following active write (address hold time is longer that data hold time so min ...

Page 86

... CX82100 Home Network Processor Data Sheet 5.2 Host Master Mode Register Memory Map Host Master Mode registers are identified in Table 5-7. Table 5-7. Host Master Mode Registers Register Label HST_CTRL Host Control Register HST_RWST Host Master Mode Read-Wait-State Control Register HST_WWST Host Master Mode Write-Wait-State Control ...

Page 87

... CX82100 Home Network Processor Data Sheet 5.3 Host Master Mode Registers 5.3.1 Host Control Register (HST_CTRL: 0x002D0000) Bit(s) Type Default 31:12 11 R/W 1'b0 DMA_SRC_ADDR_INC_DISABLE 10 R/W 1'b0 DMA_DST_ADDR_INC_DISABLE 9:8 RW 2’b00 HDMA_MODE_SEL 1’b0 EN_BLOCK_ARM 1’b0 RUN_MAP 3:2 RW 2’b10 XDM_SZ 1:0 RW 2’b00 HST_HIRQ Conexant Proprietary and Confidential Information ...

Page 88

... CX82100 Home Network Processor Data Sheet 5.3.2 Host Master Mode Read-Wait-State Control Register (HST_RWST: 0x002D0004) Bit(s) Type Default 31:25 24:20 RW 5’b00111 HST_RWS4 19:5 4:0 RW 5’b00111 HST_RWS0 5.3.3 Host Master Mode Write-Wait-State Control Register) (HST_WWST: 0x002D0008) Bit(s) Type Default 31:25 24:20 RW 5’b00111 HST_WWS4 19:5 4:0 RW 5’b00111 HST_WWS0 5.3.4 Host Master Mode Transfer Control Register (HST_XFER_CNTL: 0x002D000C) ...

Page 89

... CX82100 Home Network Processor Data Sheet 5.3.6 Host Master Mode Read Control Register 2 (HST_READ_CNTL2: 0x002D0014) Bit(s) Type Default 31:28 RW 4’b0 HRcs4_Tas 27:16 15:12 RW 4’b0 HRcs4_Tah 11:0 5.3.7 Host Master Mode Write Control Register 1 (HST_WRITE_CNTL1: 0x002D0018) Bit(s) Type Default 31:28 RW 4’b0 HWcs4_Tcss 27:16 15:12 RW 4’b0 HWcs4_Tcsh 11:0 5.3.8 Host Master Mode Write Control Register 2 (HST_WRITE_CNTL2: 0x002D001C) ...

Page 90

... CX82100 Home Network Processor Data Sheet 5.3.10 Host Master Mode Peripheral Handshake (MSTR_HANDSHAKE: 0x002D0024) (CX82100-41/-42) Bit(s) Type Default 31 1’b0 Mstr_handshake4 3 1’b0 Mstr_handshake0 5.3.11 Host Master Mode DMA Source Address (HDMA_SRC_ADDR: 0x002D0028) Bit(s) Type Default 31:24 23:0 RW 24’b0 HDma_source_addr 5.3.12 Host Master Mode DMA Destination Address (HDMA_DST_ADDR: 0x002D002C) ...

Page 91

... CX82100 Home Network Processor Data Sheet 6 External Memory Controller Interface Description 6.1 PC100 Compliant SDRAM Interface The External Memory Controller (EMC) provides a 16-bit interface to support external SDRAM. Figure 6-1 shows a typical SDRAM functional block diagram. Note that the actual SDRAM design varies from vendor to vendor. Figure 6-1 also shows an Intel PC100 compliant interface between the EMC and the SDRAM ...

Page 92

... CX82100 Home Network Processor Data Sheet Table 6-1. EMC SDRAM Interface Signal Descriptions Pin Name I/O Signal Name MD[15:0] I/O Memory Data MA[11:0] O Memory Address MB[1:0] O Bank Address MM[1:0] O Memory Mask MRAS# O Row Address Strobe MCAS# O Column Address Strobe MWE# O Memory Write Enable MCS# O Memory Chip Select MCKE ...

Page 93

... CX82100 Home Network Processor Data Sheet 6.2 Available Vendor SDRAM ICs and Features Although the EMAC is not fully PC100 compliant due to the fact that both the CAS# latency and the burst length are hard wired, many other PC100 compliant vendor SDRAMs are usable for the EMAC design. Table 6-3 lists some of these SDRAMs and their corresponding features and access timings ...

Page 94

... CX82100 Home Network Processor Data Sheet 6.3 Supported Configurations Table 6-4 lists supported SDRAM configurations. There are only one or two memory ICs at most that reside on the external SDRAM bus (e.g., two SDRAMs are required to get 4 MB). This bus is not shared with any other external function. Since the EMC buffers write data phases, this pipelined activity implies that the SDRAM bus can be busy concurrently with asynchronous and independent host bus transfers ...

Page 95

... CX82100 Home Network Processor Data Sheet 6.7 Read No acceleration is provided for read accesses. Multiple memory banks allow multiple rows to be active simultaneously. This reduces the need for precharge and activate cycles, allowing a faster aggregate throughput. 6.8 Write A 2-dword buffer is provided to speed up random and DMA write accesses. ...

Page 96

... CX82100 Home Network Processor Data Sheet 6.10 EMC I/O Clock Interface and Timing The EMC I/O clock interface is illustrated in Figure 6-2. The EMC I/O timing is illustrated in Figure 6-3. Figure 6-2. EMC Clocking Interface CLKGEN BCLK BCLK MODULE asb_sdram HNP Figure 6-3. EMC I/O Timing BCLK M CLK Notes tck-q + tdsm + tpo ...

Page 97

... CX82100 Home Network Processor Data Sheet 6.11 SRAM Interface The HNP EMC can alternatively interface to SRAM memory. The SDRAM associated pins are used for this interface and are multiplexed to either interface to SDRAM or SRAM. SDRAM or SRAM interface is controlled by the EMCR register and allows for different external sizes and up to two SRAM devices ...

Page 98

... CX82100 Home Network Processor Data Sheet 6.12 EMC Register The EMC register is identified in Table 6-7. Table 6-7. EMC Register Register Label EMCR External Memory Control Register 6.12.1 External Memory Control Register (EMCR: 0x00350010) Bit(s) Type Default Name 7:6 RW 2’b00 SRWSC 5:4 RW 2’b00 SRCSEL2 3:2 RW 2’b00 ...

Page 99

... CX82100 Home Network Processor Data Sheet 7 Ethernet Media Access Control Interface Description The HNP implements the Ethernet Media Access Control (EMAC) as defined in Reference [4]. Also implemented is the MII interface to the physical layer as defined in Reference [5]. In the OSI reference model as shown in Figure 7-1, the lowest layer is Physical and the next layer up is Data Link ...

Page 100

... CX82100 Home Network Processor Data Sheet 7.1 MAC Frame Format Figure 7-2 shows the MAC frame format supported by the HNP (see Section 3.1.1 of Reference [4]). As depicted in the figure, the bytes of a frame are transmitted from top to bottom. The bits of each byte in each field (with the exception of the FCS) are transmitted from the LSb to MSb (i ...

Page 101

... CX82100 Home Network Processor Data Sheet 7.2 Parameterized Values Used in Implementation Table 7-1 shows the values of the standard parameters used in the EMAC implementation. These parameters are defined in sections 4.4.2.1 of Reference [4] and 4.4.2.3 of Reference [5]. The value specified for the Interframe Gap (IFG) parameter determines the speed of the Ethernet defined µs for 1 Mb/s implementation, 9.6 µ ...

Page 102

... CX82100 Home Network Processor Data Sheet 7.3 EMAC Functional Features The EMAC block supports the MAC sublayer of the IEEE 802.3 and allows connected to an IEEE 802.3 10/100 Mbps (100BASE-T and 10BASE-T) MII compatible EPHY device. The EMAC block supports the following features: • ...

Page 103

... CX82100 Home Network Processor Data Sheet Full-duplex operation allows simultaneous transmission and reception of data, which can effectively double data throughput 200 Mb/s. In full-duplex mode, the HNP starts transmitting a frame provided that IFG duration time has elapsed since its previous transmission. Since there is no collision in full-duplex mode, the transmission always ends successfully ...

Page 104

... CX82100 Home Network Processor Data Sheet 7.4 EMAC Architecture Block diagram of the EMAC unit is shown in Figure 7-3. Figure 7-3. EMAC Functional Block Diagram DMA APB Interface HNP The EMAC module interfaces with the DMA controller through the DMA interface block. The APB address is decoded in this block. Tx Buffer Manager (TBM) and Rx Buffer Manager (RBM) blocks control the MAC Transmitter and MAC Receiver, respectively ...

Page 105

... CX82100 Home Network Processor Data Sheet 7.5 Media Independent Interface (MII) The MII provides a port for transmit and receive data that is media independent, multi- vendor interoperable, and supports all data rates and physical standards. The port consists of data paths that are 4 bits wide in each direction as well as control and management signals ...

Page 106

... CX82100 Home Network Processor Data Sheet 7.6 EMAC Interrupts The EMAC provides three interrupts each for EMAC1 and EMAC2: • Int_EMAC#{x}_ERR (diagnostics/exception interrupt) • Int_DMAC_EMAC#{x}_RX (packet received interrupt) • Int_DMAC_EMAC#{x}_TX (transmission complete interrupt) where {x} indicates the EMAC number (1 or 2). ...

Page 107

... CX82100 Home Network Processor Data Sheet 7.7 TMAC Architecture Before the host requests transmission of a frame, it constructs the data (LLC data) field of the frame in memory. The TMAC appends a preamble and a SFD to the beginning of the frame. Using information from the descriptor, TMAC also appends a PAD at the end of the data field of sufficient length to ensure that the transmitted frame length satisfies a minimum frame ...

Page 108

... CX82100 Home Network Processor Data Sheet Figure 7-5. EMAC Transmit Frame Structure W ritten ARM ARM ARM TM AC ARM Conexant Proprietary and Confidential Information 7-10 4 Bytes Status (TSTAT Frame #N) 0x00000000 Descriptor (TDES Frame #N) Data (Frame #N) Data (Frame #N) Next DMA Ptr (Frame #N) Next DMA Cnt (Frame #N) ...

Page 109

... CX82100 Home Network Processor Data Sheet 7.7.2 Transmit Descriptor The contents of the Transmit Descriptor (TDES) are described in Table 7-2. Table 7-2. Transmit Descriptor Format Bit(s) Field 31:17 Unused. 16 RDY Frame Ready Frame not ready to be transmitted Frame ready to be transmitted. 15:4 TLEN Transmit Frame Length. Transmit frame length in bytes. Range is 0–4095. This includes the preamble, SFD, DA, SA, length, and data to transmit ...

Page 110

... CX82100 Home Network Processor Data Sheet 7.7.3 Transmit Status (TSTAT) The contents of the Transmit Status (TSTAT) are described in Table 7-3. Table 7-3. Transmit Status Format Bit(s) Default Type 31 1’b0 TDN 30 1’b0 TU 29:21 20:17 4’ 1’b0 ** TOF 15 1’b0 ** TUF 14 1’ 1’ ...

Page 111

... CX82100 Home Network Processor Data Sheet Bit(s) Default Type 7 1’b0 ** NCRS 6 1’b0 ** LCRS 5 1’ C16 4 1’ 3:0 4’ This field resets to its default value at the start of every transmit attempt (successful or unsuccessful termination) ** This field resets to its default value after a successful transmit. ...

Page 112

... CX82100 Home Network Processor Data Sheet 7.7.4 Sequence of Transmitter DMA Operation TMAC DMA operation is illustrated in Figure 7-6. Figure 7-6. TMAC DMA Operation for Channel { Host assembles the frame to be transmitted in linked list structure and writes the T DES Host programes the base pointer DMAC_{x}_PTR1 and ...

Page 113

... CX82100 Home Network Processor Data Sheet 7.8 RMAC Architecture 7.8.1 Support for the Detection of Invalid MAC Frames As defined in the 802.3 specification, an invalid MAC frame meets at least one of the following conditions: • The frame length is inconsistent with the length field. • The frame length is not an integral number of bytes. ...

Page 114

... CX82100 Home Network Processor Data Sheet the LLC sublayer along with a status code indicating reception_complete or reception_too_long (longer than 1518 bytes). To support this requirement, address filtering (see Section 7.8. used. Address filtering is very computation intensive since it is required to be performed on every packet on the Ethernet, regardless of its intended destination. Address filtering will be supported in the RMAC hardware for " ...

Page 115

... CX82100 Home Network Processor Data Sheet Table 7-4. Setup Frame Buffer Format Entry No Note that any mix of physical (i.e., unicast: the first bit of the address is 0) and logical (i.e., multicast or group: the first bit of the address is 1) addresses can be used. Unused addresses should be duplicated with one of the valid addresses ...

Page 116

... CX82100 Home Network Processor Data Sheet Imperfect Address Filtering The HNP system can store 512 bits serving as hash bucket heads to support "multicasting". The purpose of multicasting is to allow a group of nodes in a network to receive the same message. Each node can maintain a list of multicast addresses that it will respond to ...

Page 117

... CX82100 Home Network Processor Data Sheet Table 7-5 shows the format for the setup frame involving multicast address filters. Note that one physical address filter is included in this setup frame. This is usually the address of the node itself. Table 7-5. Imperfect Address Filtering Setup Frame Format Entry No ...

Page 118

... CX82100 Home Network Processor Data Sheet Figure 7-9. Imperfect Address Filtering 47 IG Example of an Imperfect Address Filtering Setup Frame Table 7-6 displays seven multicast addresses to be filtered imperfectly and one unicast address to be filtered perfectly. The corresponding setup frame is displayed in Figure 7-10. Table 7-6. Hash Index Generated Using Ethernet CRC Algorithm ...

Page 119

... CX82100 Home Network Processor Data Sheet Figure 7-10. Example of Imperfect Filtering Setup Frame Im perfect Filtering (1) A3-C5-62-3F-25-87 (3) E7-C1-96-36-89-DD (5) 9D-48-4D-FD-CC-0A (7) AB-46-0A-55-2D-7E Setup Fram e in Host Buffer (Little-Endian) Byte No ...

Page 120

... CX82100 Home Network Processor Data Sheet Address Filtering Modes Eight different address filtering modes are supported in the HNP. These modes are configured through the E_NA_PM, E_NA_PR, E_NA_IF, E_NA_HO, and E_NA_HP bits of the Network Access Register (see Section 7.11.3). Table 7-7 lists the combination of these bits to select the desired address filtering mode ...

Page 121

... CX82100 Home Network Processor Data Sheet Promiscuous Filtering Mode. RMAC supports the reception of all good frames on the network, regardless of their destination. This mode is typically used for network monitoring. Pass All Multicast Filtering Mode. RMAC supports the reception of only multicast frames. Pass All Multicast + 16 Perfect Filtering Mode. This mode passes multicast frames and frames with addresses matching 1 of the 16 addresses in the setup frame ...

Page 122

... CX82100 Home Network Processor Data Sheet Table 7-8. Definition of RMAC Receive Status Bit(s) Default Name 63-60 Reserved. 59-52 0 CRC No. of CRC Errors. The number of errors accumulated between good frames received. Range = 0–255. 51-48 0 ALN No. of Alignment Errors. The number of alignment errors accumulated between good frames. Range = 0–15. ...

Page 123

... CX82100 Home Network Processor Data Sheet Bit(s) Default Name 3 1 Always Dribble Bit CRC Error. FIFO Overflow Conexant Proprietary and Confidential Information 101306C Description 0 = Packet length is an integer multiple of 8 bits Packet length is not an integer multiple of 8 bits. ...

Page 124

... CX82100 Home Network Processor Data Sheet 7.8.6 Sequence of Receiver DMA Operation The sequence of receiver DMA operation is illustrated in Figure 7-11. Figure 7-11. Sequence of Receiver DMA Operation wait for E_NA_SR assertion RMAC Updates the MIB counters and aborts the frame by sending DMA_RELD command to DMAC Conexant Proprietary and Confidential Information ...

Page 125

... CX82100 Home Network Processor Data Sheet 7.9 7-Wire Serial Interface (7-WS) This mode is enabled by setting bit 7 of the EMAC x Network Access register (E_NA_{x}). In this mode the MII interface works in serial mode and is designed to interface to Conexant’s CX24611 HomePNA 2.0 PHY/AFE or to any other GPSI interface (AMD's " ...

Page 126

... CX82100 Home Network Processor Data Sheet 7.10 EMAC Register Memory Map EMAC registers are identified in Table 7-10. Table 7-10. EMAC Registers Register Label E_DMA_1 EMAC 1 Source/Destination DMA Data Register E_NA_1 EMAC 1 Network Access Register E_Stat_1 EMAC 1 Status Register E_IE_1 EMAC 1 Interrupt Enable Register E_LP_1 ...

Page 127

... CX82100 Home Network Processor Data Sheet 7.11 EMAC Registers 7.11.1 EMAC x Source/Destination DMA Data Register (E_DMA_1: 0x00310000 and E_DMA_2: 0x00320000) E_DMA_1 and E_DMA_2 are the EMAC source/destination DMA data registers for EMAC1 and EMAC2, respectively (used by the EMAC DMA transmit channel). Bit(s) Type ...

Page 128

... CX82100 Home Network Processor Data Sheet 7.11.3 EMAC x Network Access Register (E_NA_1: 0x00310004 and E_NA_2: 0x00320004) E_NA_1 and E_NA_2 are the EMAC Network Access registers for EMAC1 and EMAC2, respectively. Bit(s) Type Default 31 RW 1’b1 E_NA_RTX 30 RW 1’b0 E_NA_STOP 29: 1’b0 E_NA_HP ...

Page 129

... CX82100 Home Network Processor Data Sheet Bit(s) Type Default 15 RW 1’b0 E_NA_JBD 14 RW 1’b0 E_NA_HUJ 13 RW 1’b0 E_NA_JCLK 12 RW 1’b0 E_NA_SB 11 RW 1’b0 E_NA_FD 10:9 RW 2’b00 E_NA_OM 8 RW 1’b0 E_NA_FC 7 RW 1’b0 E_NA_HLAN 6 RW 1’b0 E_NA_SR 5 RW 1’b0 E_NA_NS 4 RW 1’b0 ...

Page 130

... CX82100 Home Network Processor Data Sheet Bit(s) Type Default 3 RW 1’b0 E_NA_RWD 2 1’b0 E_NA_STRT Conexant Proprietary and Confidential Information 7-32 Name Receive Watchdog Disable the receiving packet's length is longer than 2560 bytes, the watchdog timer will be expired Disable the watchdog timer. ...

Page 131

... CX82100 Home Network Processor Data Sheet 7.11.4 EMAC x Status Register (E_Stat_1: 0x00310008 and E_Stat_2: 0x00320008) E_Stat_1 and E_Stat_2 are the EMAC Status registers for EMAC1 and EMAC2, respectively. Writing to this register will clear all of its bits (as denoted by RW*). Bit(s) Type Default 31 RW* 1’ ...

Page 132

... CX82100 Home Network Processor Data Sheet Bit(s) Type Default 9 RW* 1’b0 E_S_TF 8 RW* 1’b0 E_S_TJT 7 RW* 1’b0 E_S_NCRS 6 RW* 1’b0 E_S_LCRS 5 RW* 1’b0 E_S_16 4 RW* 1’b0 E_S_LC 3:0 RW* 4’b0 E_S_CC 7.11.5 EMAC x Receiver Last Packet Register (E_LP_1: 0x00310010 and E_LP_2: 0x00320010) E_LP_1 and E_LP_2 are the EMAC Receiver Last Packet registers for EMAC1 and EMAC2, respectively ...

Page 133

... CX82100 Home Network Processor Data Sheet 7.11.6 EMAC x Interrupt Enable Register (E_IE_1: 0x0031000C and E_IE_2: 0x0032000C) E_IE_1 and E_IE_2 are the EMAC Error Interrupt Enable registers for EMAC1 and EMAC2, respectively. Bit(s) Type Default 31: 1’b0 E_IE_NI 15 RW 1’b0 E_IE_RW 14 RW 1’b0 ...

Page 134

... CX82100 Home Network Processor Data Sheet 7.11.7 EMAC x MII Management Interface Register (E_MII_1: 0x00310018 and E_MII_2: 0x00320018) E_MII_1 and E_MII_2 are the EMAC MII Management Interface registers for EMAC1 and EMAC2, respectively. Bit(s) Type Default 31 1’b0 E_MDIP 3 RW 1’b1 E_MM 2 RW 1’ ...

Page 135

... CX82100 Home Network Processor Data Sheet 8 USB Interface Description The USB Interface (or UDC Core) consists of three major functions: USB Controller (USBC), APB/DMA Interface (I/F), and USB Differential Transceiver (Figure 8-1). The USBC includes the following functions: • Phase Locked Loop (PLL) Block. The PLL Block extracts the USB clock and data from the USB cable ...

Page 136

... CX82100 Home Network Processor Data Sheet Figure 8-1. Block Diagram of the USB Interface APB APB/DMA Interface (I/F) HNP Conexant Proprietary and Confidential Information 8-2 USB Interface (UDC Core) USB Controller (USBC) USB Bridge Layer Serial Interface (UBL) Block (SIE) Block Protocol Layer Transm itter ...

Page 137

... CX82100 Home Network Processor Data Sheet 8.1 UDC Data Path The UDC data path supports USB transmit and receive data. 8.1.1 USB Transmit Data Path (Endpoint IN Channel) The USB transmit data flow is illustrated in Figure 8-2. Figure 8-2. USB Transmit Data Flow data payload xxx xxx ...

Page 138

... CX82100 Home Network Processor Data Sheet 8.1.2 USB Receive Data Path (Endpoint OUT Channel) The USB receive data flow is illustrated in Figure 8-3. Figure 8-3. USB Receive Data Flow to APB/ DMA I/F Serial-to- Data UBL Parallel Buffer Conversion Conexant Proprietary and Confidential Information 8-4 SYNC Pattern ...

Page 139

... CX82100 Home Network Processor Data Sheet 8.2 USB Data Flow USB data can be identified as control, bulk, or interrupt data in the HNP. Control data is usually structured as a command phase initiated by the USB host, followed by data either provided by the device (IN), i.e., HNP (IN), or sent the host (OUT), followed in turn by a status phase which serves as an acknowledgement of transfer ...

Page 140

... CX82100 Home Network Processor Data Sheet 8.3 UDC Core The USB Core includes the endpoint buffers and associated processing. 8.3.1 Endpoint Buffer Format The UDC stores all the endpoint configuration information for each endpoint that the HNP supports. Each endpoint configuration is stored in a separate Buffer called EndPtBuf. The UDC Core has defined the logical and physical endpoints for its implementation. A “ ...

Page 141

... CX82100 Home Network Processor Data Sheet 8.3.2 Example of Endpoint Buffer Encoding As shown in Figure 8-4, the HNP supports one configuration, one interface with no alternate setting and four logical endpoints (Endpoints and 4). The first three endpoints are bidirectional endpoints and the fourth is an interrupt endpoint, therefore there are nine physical endpoints total (including controlled Endpoint 0) ...

Page 142

... CX82100 Home Network Processor Data Sheet 8.3.3 Loading of the EndPtBuf Configurations The endpoint configuration in the UDC Core is accomplished by writing to the U_CFG register the same byte-wise data that the UDC Core expects. The target of these configuration writes are the endpoint buffers which have the format shown in Table 8-1. ...

Page 143

... CX82100 Home Network Processor Data Sheet Figure 8-5. Loading of the EndPtBuf Configurations 39:32 31:24 23:16 B#0 B#1 B#2 EndPtBuf0 EndPtBuf1 B#5 B#6 B#7 B#10 B#11 B#12 EndPtBuf2 .... .... .... EndPtBuf3 B#35 B#36 B#37 EndPtBuf4 8.3.4 USB Command Handling The UDC handles and decodes all USB Standard Commands defined in the USB Specification Rev. 1.1. The UDC returns a STALL HandShake if it receives an unsupported or invalid Standard Command. The UDC will forward all controlled ...

Page 144

... CX82100 Home Network Processor Data Sheet 8.4 USB DMA Interface DMAC interfaces with the USB device through addressed writes/reads that conform to the common DMA protocol. 8.4.1 DMA Receive Channel The DMA channel supporting receive OUT endpoints is illustrated in Figure 8-6. The endpoint data is described in Table 8-3. ...

Page 145

... CX82100 Home Network Processor Data Sheet Table 8-4. Status qword for Receive (OUT) Endpoint APB Buffers Bit(s) 63:16 15 14:12 11:8 7 6:0 After the DMA Channel 12 pointer and counter (circular RX DMA Buffer) and EP_OUT_RX_BUFSIZE register are initialized, the RV_INIT bit in U_CTR1 register is set and cleared (in the next instruction) before enabling endpoint OUT operation. This bit is not set again until new RX DMA buffer setting is required and only when all receive endpoints have been disabled ...

Page 146

... CX82100 Home Network Processor Data Sheet 8.4.2 DMA Transmit Channel The DMA channels supporting USB transmit IN endpoints are illustrated in Figure 8-6. The endpoint data is described in Table 8-3. Figure 8-7. DMA Channels for USB Transmit IN Endpoints ARM Host Table 8-5. DMA Channels for USB Transmit IN Endpoints Endpoint No ...

Page 147

... CX82100 Home Network Processor Data Sheet The descriptor also contains the count of bytes to be sent in the current packet and the logical endpoint address corresponding to that endpoint. If there is a mismatch between the endpoint address from the buffer descriptor and the corresponding endpoint descriptor in UDC Core, the " ...

Page 148

... CX82100 Home Network Processor Data Sheet 8.5 Interrupt Endpoint The interrupt endpoint is different from the other endpoints in that it does not get its data from the TX DMA buffers or there DMA channel available for interrupt endpoint. The interrupt endpoint relies on firmware writes to the U_IDAT register for the interrupt data ...

Page 149

... CX82100 Home Network Processor Data Sheet 8.7 USB Register Memory Map USB registers are identified in Table 8-9. Table 8-9. USB Registers Register Label U0_DMA USB Source/Destination DMA Data Register 0 U1_DMA USB Source/Destination DMA Data Register 1 U2_DMA USB Source/Destination DMA Data Register 2 U3_DMA USB Source/Destination DMA Data ...

Page 150

... CX82100 Home Network Processor Data Sheet 8.8 USB Registers 8.8.1 USB Source/Destination DMA Data Register 0 (U0_DMA: 0x00330000) U0_DMA is the USB source/destination DMA data register (used by DMA Transmit Channel 13 hardware for USB Endpoint 0 IN channel). Not used by firmware. Bit(s) Type Default 63:0 RWp 64'bx U0_DMA 8.8.2 USB Source/Destination DMA Data Register 1 (U1_DMA: 0x00330008) U1_DMA is the USB source/destination DMA data register (used by DMA Transmit Channel #11 hardware for USB Endpoint 1 IN channel) ...

Page 151

... CX82100 Home Network Processor Data Sheet 8.8.5 USB Destination DMA Data Register (UT_DMA: 0x00330020) UT_DMA is the USB destination DMA data register (used by the USB DMA Receive hardware Channel #12). Not used by firmware. Bit(s) Type Default 63:0 RO 64'bx UT_DMA 8.8.6 USB Configuration Data Register (U_CFG: 0x00330024) U_CFG is the USB configuration data register. ...

Page 152

... CX82100 Home Network Processor Data Sheet 8.8.8 USB Control Register 1 (U_CTR1: 0x0033002C) Bit(s) Type Default 31 RW 1'b0 USB_IE 30 RW 1'b1 USB_RESET 29 RW 1'b0 AI_RESUME 28 RW 1’b0 RV_INIT 27:16 RW 13' 1'b0 EP3_IN_DMA_RESET 14 RW 1'b0 EP2_IN_DMA_RESET 13 RW 1'b0 EP1_IN_DMA_RESET Conexant Proprietary and Confidential Information 8-18 Name Global USB Interrupt Enable Disable all USB related interrupts. ...

Page 153

... CX82100 Home Network Processor Data Sheet Bit(s) Type Default 12 RW 1'b0 EP0_IN_DMA_RESET 11 RW 1’b0 XVER_SLEEP 10 RW 1’b0 INTR_EN 9 RW 1’b0 EP3I_EN 8 RW 1’b0 EP2I_EN 7 RW 1’b0 EP1I_EN 6 RW 1’b0 EP0I_EN 5 RW 1’b0 EP3O_EN 4 RW 1’b0 EP2O_EN 3 RW 1’b0 EP1O_EN 2 RW 1’b0 EP0O_EN ...

Page 154

... CX82100 Home Network Processor Data Sheet 8.8.9 USB Control Register 2 (U_CTR2: 0x00330030) Bit(s) Type Default 27:24 RW 4’b0 INTR_ADDR 23:20 RW 4’b0 EP3I_ADDR 19:16 RW 4’b0 EP2I_ADDR 15:12 RW 4’b0 EP1I_ADDR 11:8 RW 4’b0 EP3O_ADDR 7:4 RW 4’b0 EP2O_ADDR 3:0 RW 4’b0 EP1O_ADDR Conexant Proprietary and Confidential Information 8-20 Name Endpoint 4 IN Address ...

Page 155

... CX82100 Home Network Processor Data Sheet 8.8.10 USB Control Register 3 (U_CTR3: 0x00330034) Bit(s) Type Default 29 RW 1’b0 EP3O_STALL_EN 28 RW 1’b0 EP2O_STALL_EN 27 RW 1’b0 EP1O_STALL_EN 26 RW 1’b0 EP0O_STALL_EN 25 RW 1’b0 EP3I_STALL_EN 24 RW 1’b0 EP2I_STALL_EN 23 RW 1’b0 EP1I_STALL_EN 22 RW 1’b0 EP0I_STALL_EN 21 RW 1’b0 INTR_STALL_EN ...

Page 156

... CX82100 Home Network Processor Data Sheet 8.8.11 USB Status (U_STAT: 0x00330038 interrupt status bit in this register is set by the UDC, the USB Interrupt bit in the Interrupt Status Register (INT_Stat) is set if the corresponding enable bit in the U_IER register is set. Writing bit location will clear the interrupt status bit; writing a 0 has no effect ...

Page 157

... CX82100 Home Network Processor Data Sheet Bit(s) Type Default 25 RR 1'b0 UDC_UsbReset_INT 24 RR 1'b0 UDC_Sof_INT 23 RR 1'b0 USB_SUSPEND_INT 22 RR 1’b0 USB_RESUME_INT 21 RR 1’b0 EP3I_INVLDHDR_INT 20 RR 1’b0 EP2I_INVLDHDR_INT 19 RR 1’b0 EP1I_INVLDHDR_INT 18 RR 1’b0 EP0I_INVLDHDR_INT 17 RR 1’b0 INTR_NAK_INT 16 RR 1’b0 INTR_ERRCNT_INT Conexant Proprietary and Confidential Information ...

Page 158

... CX82100 Home Network Processor Data Sheet Bit(s) Type Default 15 RR 1’b0 EP3I_ERRCNT_INT 14 RR 1’b0 EP2I_ERRCNT_INT 13 RR 1’b0 EP1I_ERRCNT_INT 12 RR 1’b0 EP0I_ERRCNT_INT 11 RR 1’b0 INTRNEXT_INT 10 RR 1’b0 INTRDN_INT 9 RR 1’b0 EP3I_INT 8 RR 1’b0 EP2I_INT 7 RR 1’b0 EP1I_INT 6 RR 1’b0 EP0I_INT 5 RR 1’b0 ...

Page 159

... CX82100 Home Network Processor Data Sheet 8.8.12 USB Interrupt Enable Register (U_IER: 0x0033003C) Writing bit location will enable setting of the USB Interrupt bit in the Interrupt Status Register (INT_Stat) if the corresponding interrupt status bit is set in the USB_STAT register. Writing bit location will disable setting the USB Interrupt bit in the INT_Stat register due to the corresponding interrupt status bit ...

Page 160

... CX82100 Home Network Processor Data Sheet 8.8.13 USB Status Register 2 (U_STAT2: 0x00330040 interrupt status bit in this register is set by the UDC, the USB Interrupt bit in the Interrupt Status Register (INT_Stat) is set if the corresponding enable bit in the U_IER2 register is set. Writing bit location will clear the interrupt status bit; writing a 0 has no effect ...

Page 161

... CX82100 Home Network Processor Data Sheet Bit(s) Type Default 16 RR 1'b0 EP2O_STALL_CLR_INT 15 RR 1'b0 EP1O_STALL_CLR_INT 14 RR 1'b0 EP0O_STALL_CLR_INT 13 RR 1'b0 EP3I_STALL_CLR_INT 12 RR 1'b0 EP2I_STALL_CLR_INT 11 RR 1'b0 EP1I_STALL_CLR_INT 10 RR 1'b0 EP0I_STALL_CLR_INT 9 RR 1'b0 INTR_STALL_CLR_INT 8 RR 1'b0 EP3O_STALL_INT 7 RR 1'b0 EP2O_STALL_INT 6 RR 1'b0 EP1O_STALL_INT 5 RR 1'b0 EP0O_STALL_INT 4 RR 1'b0 EP3I_STALL_INT 3 RR 1'b0 EP2I_STALL_INT 2 RR 1'b0 EP1I_STALL_INT 1 RR 1'b0 EP0I_STALL_INT ...

Page 162

... CX82100 Home Network Processor Data Sheet 8.8.14 USB Interrupt Enable Register 2 (U_IER2: 0x00330044) Writing bit location will enable setting of the USB Interrupt in the Interrupt Status Register (INT_Stat) if the corresponding interrupt status bit is set in the USB_STAT2 register. Writing a 0 will disable setting the USB Interrupt bit in the INT_Stat register due to the corresponding interrupt status bit ...

Page 163

... CX82100 Home Network Processor Data Sheet 8.8.15 UDC Time Stamp Register (UDC_TSR: 0x0033008C) Bit(s) Type Default 10:0 RO 11'b0 UDC_TimeStamp 8.8.16 UDC Status Register (UDC_STAT: 0x00330090) Note: Bit(s) Type Default 11:9 RO 3'b0 UDC_AltIntfVal 8:7 RO 2'b0 UDC_InterfaceVal 6:5 RO 2'b0 UDC_ConfigVal 4 RO 1'b0 TxenL 3 RO 1'b0 TXDMns 2 RO 1'b0 TXDPls 1 RO 1'b0 DMNS 0 RO 1'b0 DPLS Conexant Proprietary and Confidential Information ...

Page 164

... CX82100 Home Network Processor Data Sheet 8.9 USB DMA Control Registers 8.9.1 EP0_IN Transmit Increment Register (EP0_IN_TX_INC: 0x00330048) Bit(s) Type Default 7:0 RW 8'b0 EP0_IN_TX _INC 8.9.2 EP0_IN Transmit Pending Register (EP0_IN_TX_PEND: 0x0033004C) Bit(s) Type Default 7:0 RO 8'b0 EP0_IN_TX _PEND 8.9.3 EP0_IN Transmit qword Count Register (EP0_IN_TX_QWCNT: 0x00330050) Bit(s) Type ...

Page 165

... CX82100 Home Network Processor Data Sheet 8.9.5 EP1_IN Transmit Pending Register (EP1_IN_TX_PEND: 0x00330058) Bit(s) Type Default 7:0 RO 8'b0 EP1_IN_TX _PEND 8.9.6 EP1_IN Transmit qword Count Register (EP1_IN_TX_QWCNT) Bit(s) Type Default 3:0 RO 4'b0 EP1_IN_TX _QWCNT 8.9.7 EP2_IN Transmit Increment Register (EP2_IN_TX_INC: 0x00330060) Bit(s) Type Default 7:0 RW 8'b0 EP2_IN_TX _INC 8.9.8 EP2_IN Transmit Pending Register (EP2_IN_TX_PEND: 0x00330064) ...

Page 166

... CX82100 Home Network Processor Data Sheet 8.9.9 EP2_IN Transmit qword Count Register (EP2_IN_TX_QWCNT) Bit(s) Type Default 3:0 RO 4'b0 EP2_IN_TX _QWCNT 8.9.10 EP3_IN Transmit Increment Register (EP1_IN_TX_INC: 0x0033006C) Bit(s) Type Default 7:0 RW 8'b0 EP3_IN_TX _INC 8.9.11 EP3_IN Transmit Pending Register (EP3_IN_TX_PEND: 0x00330070) Bit(s) Type Default 7:0 RO 8'b0 EP3_IN_TX _PEND 8.9.12 EP3_IN Transmit qword Count Register (EP3_IN_TX_QWCNT: 0x00330074) ...

Page 167

... CX82100 Home Network Processor Data Sheet 8.9.13 EP_OUT Receive Decrement Register (EP_OUT_RX_DEC: 0x00330078) Bit(s) Type Default 7:0 RW 8'b0 EP_OUT_RX _DEC 8.9.14 EP_OUT Receive Pending Register (EP_OUT_RX_PEND: 0x0033007C) Bit(s) Type Default 7:0 RO 8'b0 EP_OUT_RX_PEND 8.9.15 EP_OUT Receive Buffer Size Register (EP_OUT_RX_BUFSIZE: 0x00330084) Bit(s) Type Default 7:0 RW 8'b0 EP_OUT_RX_BUFSIZE 8.9.16 EP_OUT Receive qword Count Register (EP_OUT_RX_QWCNT: 0x00330080) ...

Page 168

... CX82100 Home Network Processor Data Sheet 8.9.17 USB Receive DMA Watchdog Timer Register (USB_RXTIMER: 0x00330094) Bit(s) Type Default 15:0 RW 16'b0 USB_RXTIMER 8.9.18 USB Receive DMA Watchdog Timer Counter Register (USB_RXTIMERCNT: 0x00330098) Bit(s) Type Default 23:0 RO 24'b0 USB_RXTIMERCNT 8.9.19 EP_OUT Receive Pending Interrupt Level Register (EP_OUT_RX_PENDLEVEL: 0x0033009C) Table 8-10. EP_OUT Receive Pending Level Register ...

Page 169

... CX82100 Home Network Processor Data Sheet 8.9.20 USB Control-Status Register (U_CSR: 0x00330088) Bit(s) Type Default 14 RO 1'b0 EP_OUT_RX_PENDISFULL 13 RO 1'b1 EP3_IN_TX_PENDISZERO 12 RO 1'b1 EP2_IN_TX_PENDISZERO 11 RO 1'b1 EP1_IN_TX_PENDISZERO 10 RO 1'b1 EP0_IN_TX_PENDISZERO 9 WO 1'b0 EP_OUT_RX_CLRQWCNT 8 WO 1’b0 EP_OUT_RX_CLRPEND 7 WO 1’b0 EP3_IN_TX_CLRQWCNT 6 WO 1'b0 EP3_IN_TX_CLRPEND 5 WO 1'b0 EP2_IN_TX_CLRQWCNT 4 WO 1'b0 EP2_IN_TX_CLRPEND 3 WO 1'b0 EP1_IN_TX_CLRQWCNT Conexant Proprietary and Confidential Information ...

Page 170

... CX82100 Home Network Processor Data Sheet Bit(s) Type Default 2 WO 1'b0 EP1_IN_TX_CLRPEND 1 WO 1'b0 EP0_IN_TX_CLRQWCNT 0 WO 1'b0 EP0_IN_TX_CLRPEND Conexant Proprietary and Confidential Information 8-36 Name Clear the Transmit Pending Register for EP1_IN effect Clear the Transmit Pending Register for EP1_IN. This bit self-clears one cycle after written. ...

Page 171

... CX82100 Home Network Processor Data Sheet 9 General Purpose Input/Output Interface Description 9.1 GPIO Pin Description The GPIO pins can be read by reading GPIO_DATA_IN{x} register. They can be driven as outputs by using GPIO_OE{x} for the pin driver enable, and GPIO_DATA_OUT{x} for the data output polarity. Each GPIO[x] pin is controlled individually by GPIO_OE{x} for the input/output direction ...

Page 172

... CX82100 Home Network Processor Data Sheet 9.2 GPIO Register Memory Map GPIO registers are identified in Table 9-1. Table 9-1. GPIO Registers Register Label GPIO_ISM1 GPIO Interrupt Sensitivity Mode Register 1 GPIO_ISM2 GPIO Interrupt Sensitivity Mode Register 2 GPIO_ISM3 GPIO Interrupt Sensitivity Mode Register 3 GPIO_OPT GPIO Option Register ...

Page 173

... CX82100 Home Network Processor Data Sheet 9.3 GPIO Registers GPIO register bits are described in this section. 9.3.1 GPIO Option Register for GPIO[39:37; 32] (GPIO_OPT: 0x003500B0) This register selects general or special purpose use for the GPIO[39:37; 32] pins. Note: Bit(s) Type Default 31 1’b0 GPIO_Sel7 6 RW 1’ ...

Page 174

... CX82100 Home Network Processor Data Sheet 9.3.2 GPIO Output Enable Register 1 for GPIO[15:14; 8:5] (GPIO_OE1: 0x003500B4) GPIO_OE1 is the output enable register for GPIO[15:14; 8:5]. Bit(s) Type Default 15:0; RW 16’b0 15 ≥ Y ≥ Bit # Bit(s) Type Default 31: 1’ 1’b0 13 1’ 1’b0 ...

Page 175

... CX82100 Home Network Processor Data Sheet 9.3.4 GPIO Output Enable Register 3 for GPIO[39:37; 32] (GPIO_OE3: 0x003500BC) GPIO_OE3 is the output enable register for GPIO[39:37; 32]. Bit(s) Type Default 7:0; RW 8’b0 7 ≥ Y ≥ Bit # Bit(s) Type Default 31 1’ 1’ 1’b1 4 1’b1 9.3.5 GPIO Data Input Register 1 for GPIO[15:14 ...

Page 176

... CX82100 Home Network Processor Data Sheet 9.3.6 GPIO Data Input Register 2 for GPIO[31; 27:24; 22:16] (GPIO_DATA_IN2: 0x003500C4) GPIO_DATA_IN2 is the data input register for GPIO[31; 27:24; 22:16]. Bit(s) Type Default 15:0; RO 16’bx 15 ≥ Y ≥ Bit # Bit(s) Type 31: 1’bx 14: 1’ 1’ 1’bx ...

Page 177

... CX82100 Home Network Processor Data Sheet 9.3.8 GPIO Data Output Register 1 for GPIO[15:14; 8:5] (GPIO_DATA_OUT1: 0x003500CC) The GPIO Data Output Register 1 contains read/write data output bits and corresponding write-only output mask bits for GPIO[15:14; 8:5]. Writing output mask bit (GPIO_DOMSKx) enables the level corresponding to associated data output bit (GPIO_DOUTx) onto the associated GPIO pin when the associated direction bit (GPIO_OEx ...

Page 178

... CX82100 Home Network Processor Data Sheet 9.3.9 GPIO Data Output Register 2 for GPIO[31; 27:24; 22:16] (GPIO_DATA_OUT2: 0x003500D0) The GPIO Data Output Register 2 contains read/write data output bits and corresponding write-only output mask bits for GPIO[31; 27:24; 22:16]. Writing output mask bit (GPIO_DOMSKx) enables the level corresponding to associated data output bit (GPIO_DOUTx) onto the associated GPIO pin when the associated direction bit (GPIO_OEx ...

Page 179

... CX82100 Home Network Processor Data Sheet 9.3.10 GPIO Data Output Register 3 for GPIO[39:37; 32] (GPIO_DATA_OUT3: 0x003500D4) The GPIO Data Output Register 3 contains read/write data output bits and corresponding write-only output mask bits for GPIO[39:32]. Writing output mask bit (GPIO_DOMSKx) enables the level corresponding to associated data output bit (GPIO_DOUTx) onto the associated GPIO pin when the associated direction bit (GPIO_OEx ...

Page 180

... CX82100 Home Network Processor Data Sheet 9.3.11 GPIO Interrupt Status Register 1 for GPIO[15:14; 8:5] (GPIO_ISR1: 0x003500D8) GPIO_ISR1 is the interrupt input status register for GPIO[15:14; 8:5]. Note: Bit(s) Type Default 15:0; RR See specific bit 15 ≥ Y ≥ Bit # Bit(s) Type Default 15 RR 1’ 1’b0 13 1’ ...

Page 181

... CX82100 Home Network Processor Data Sheet Bit(s) Type Default 15:0; RR See specific bit 15 ≥ Y ≥ Bit # Bit(s) Type Default 15 RR 1’b0 14: 1’ 1’ 1’ 1’ 1’ 1’ 1’ 1’ 1’ 1’ ...

Page 182

... CX82100 Home Network Processor Data Sheet 9.3.13 GPIO Interrupt Status Register 3 for GPIO[39:37; 32] (GPIO_ISR3: 0x003500E0) GPIO_ISR3 is the interrupt input status register for GPIO[39:37; 32]. Note: Bit(s) Type Default 7:0; RR See specific bit 7 ≥ Y ≥ Bit # Bit(s) Type Default 31 1’ 1’ 1’ ...

Page 183

... CX82100 Home Network Processor Data Sheet 9.3.14 GPIO Interrupt Enable Register 1 for GPIO[15:14; 8:5] (GPIO_IER1: 0x003500E4) GPIO_IER1 is the interrupt input enable register for GPIO[15:14; 8:5]. Note: Bit(s) Type Default 31:16; RO See specific bit 31 ≥ Y ≥ 16 Bit # 15:0; RW See specific bit 15 ≥ Y ≥ Bit # Bit(s) ...

Page 184

... CX82100 Home Network Processor Data Sheet 9.3.15 GPIO Interrupt Enable Register 2 for GPIO[31; 27:24; 22:16] (GPIO_IER2: 0x003500E8) GPIO_IER2 is the interrupt input enable register for GPIO[31:16]. Note that if an interrupt input is enabled for GPIO[X], then GPIO[X] must be configured as an input. Bit(s) Type Default 31:16; RO See specific bit 31 ≥ ...

Page 185

... CX82100 Home Network Processor Data Sheet 9.3.16 GPIO Interrupt Enable Register 3 for GPIO[39:37; 32] (GPIO_IER3: 0x003500EC) GPIO_IER3 is the interrupt input enable register for GPIO[39:37; 32]. Note: Bit(s) Type Default 31:24 23:16; RO See specific bit 23 ≥ Y ≥ 16 Bit # 15:8 7:0; RW See specific bit 7 ≥ Y ≥ Bit # Bit(s) ...

Page 186

... CX82100 Home Network Processor Data Sheet 9.3.17 GPIO Interrupt Polarity Control Register 1 for GPIO[15:14; 8:5] (GPIO_IPC1: 0x003500F0) GPIO_IPC1 is the interrupt polarity control register for GPIO[15:14; 8:5]. Bit(s) Type Default 31:16; RO See specific bit 31 ≥ Y ≥ 16 Bit # 15:0; RW See specific bit 15 ≥ Y ≥ Bit # Bit(s) ...

Page 187

... CX82100 Home Network Processor Data Sheet 9.3.18 GPIO Interrupt Polarity Control Register 2 for GPIO[31; 27:24; 22:16] (GPIO_IPC2: 0x003500F4) GPIO_IPC2 is the interrupt polarity control register for GPIO[31; 27:24; 22:16]. Bit(s) Type Default 31:16; RO See specific bit 31 ≥ Y ≥ 16 Bit # 15:0; RW See specific bit 15 ≥ Y ≥ Bit # Bit(s) ...

Page 188

... CX82100 Home Network Processor Data Sheet 9.3.19 GPIO Interrupt Polarity Control Register 3 for GPIO[39:37; 32] (GPIO_IPC3: 0x003500F8) GPIO_IPC3 is the interrupt polarity control register for GPIO[39:37; 32]. Bit(s) Type Default 31:24 23:16; RO See specific bit 23 ≥ Y ≥ 16 Bit # 15:8 7:0; RW See specific bit 7 ≥ Y ≥ Bit # Bit(s) ...

Page 189

... CX82100 Home Network Processor Data Sheet 9.3.20 GPIO Interrupt Sensitivity Mode Register 1 for GPIO[15:14; 8:5] (GPIO_ISM1: 0x003500A0) GPIO_ISM1 is the interrupt sensitive mode register for GPIO[15:14; 8:5]. Bit(s) Type Default 31:16; RO See specific bit 31 ≥ Y ≥ 16 Bit # 15:0; RW See specific bit 15 ≥ Y ≥ Bit # Bit(s) ...

Page 190

... CX82100 Home Network Processor Data Sheet 9.3.21 GPIO Interrupt Sensitivity Mode Register 2 for GPIO[31; 27:24; 22:16] (GPIO_ISM2: 0x003500A4) GPIO_ISM2 is the interrupt sensitive mode register for GPIO[31; 27:24; 22:16]. Bit(s) Type Default 31:16; RO See specific bit 31 ≥ Y ≥ 16 Bit # 15:0; RW See specific bit 15 ≥ Y ≥ Bit # Bit(s) ...

Page 191

... CX82100 Home Network Processor Data Sheet 9.3.22 GPIO Interrupt Sensitivity Mode Register 3 for GPIO[39:37; 32] (GPIO_ISM3: 0x003500A8) GPIO_ISM2 is the interrupt sensitive mode register for GPIO[39:37; 32]. Bit(s) Type Default 31:24 23:16; RO See specific bit 23 ≥ Y ≥ 16 Bit # 15:8 7:0; RW See specific bit 7 ≥ Y ≥ Bit # Bit(s) ...

Page 192

... CX82100 Home Network Processor Data Sheet Conexant Proprietary and Confidential Information 9-22 This page is intentionally blank. 101306C ...

Page 193

... CX82100 Home Network Processor Data Sheet 10 Memory to Memory Transfer Input/Output 10.1 Operation A qword buffer resides within this block to support memory to memory block transfers. Data transfer requests are issued to the DMAC via channel 7 for reading from the source buffer and channel 8 for writing to the destination buffer. The number of qwords to transfer is set by M2M_Cntl ...

Page 194

... CX82100 Home Network Processor Data Sheet Table 10-2. M2M Transfer Example 2 Byte Source Memory Destination Address to Copy: 24B Memory before Start Source Byte-Address 1 00 030201 00 FFFFFFFF 04 07060504 FFFFFFFF 08 0B0A0908 FFFFFFFF 0C 0F0E0D0C FFFFFFFF 10 13121110 FFFFFFFF 14 17161514 FFFFFFFF 18 1B1A19 18 FFFFFFFF Table 10-3. M2M Transfer Example 3 ...

Page 195

... CX82100 Home Network Processor Data Sheet 10.2 M2M Register Memory Map M2M registers are identified in Table 10-4 Table 10-4. M2M Registers Register Label M2M_DMA Memory to Memory DMA Data Register M2M_Cntl Memory to Memory DMA Transfer Control/Counter 10.3 M2M Registers 10.3.1 Memory to Memory DMA Data Register (M2M_DMA: 0x00350000) ...

Page 196

... CX82100 Home Network Processor Data Sheet Conexant Proprietary and Confidential Information 10-4 This page is intentionally blank. 101306C ...

Page 197

... CX82100 Home Network Processor Data Sheet 11 Interrupt Controller Interface Description All peripheral interrupt sources are routed through the Interrupt Controller (INTC) and reduced to one of two active low inputs to the ARM940T processor, fast interrupt (FIQ#) or regular interrupt (IRQ#), as selected in the Interrupt Level Assignment Register (INT_LA) ...

Page 198

... CX82100 Home Network Processor Data Sheet 11.2.2 Interrupt Status Register (INT_Stat: 0x00350044) Each interrupt source sets a bit in the interrupt status register (INT_Stat). These pending interrupts can be read at anytime bit in this register represents multiple interrupt sources, then it is read-only. Most bits are automatically cleared once all the corresponding interrupt sources are cleared, however, bits 19 and 20 are not automatically cleared ...

Page 199

... CX82100 Home Network Processor Data Sheet Bit Type Default 18 RR 1’b0 Int_DMAC_ERR 17: 1’b0 Int_DMAC_EMAC#1_TX 14 RR 1’b0 Int_DMAC_EMAC#1_RX 13 RR 1’b0 Int_DMAC_EMAC#2_TX 12 RR 1’b0 Int_DMAC_EMAC#2_RX 11 1’b0 Int_M2M_Dst 7 RR 1’b0 Int_HOST_ERR 6 RR 1’b0 Int_HOST 1’b0 Int_USB 3 RR 1’b0 Int_TIMER4 2 RR 1’ ...

Page 200

... CX82100 Home Network Processor Data Sheet 11.2.3 Interrupt Set Status Register (INT_SetStat: 0x00350048) This is a Write-Only register. The interrupt set status (INT_SetStat) register has 32 bits. Writing a one to a bit location of this register will cause the corresponding interrupt to occur. Writing a zero will have no effect. Only the four software interrupts defined in INT_Stat[31:28] can be triggered by using this register ...

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