cx82100 Conexant Systems, Inc., cx82100 Datasheet - Page 124

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cx82100

Manufacturer Part Number
cx82100
Description
Home Network Processor Hnp
Manufacturer
Conexant Systems, Inc.
Datasheet

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7.8.6
Figure 7-11. Sequence of Receiver DMA Operation
7-26
Sequence of Receiver DMA Operation
RMAC Updates the
MIB counters and
aborts the frame by
sending DMA_RELD
command to DMAC
Conexant Proprietary and Confidential Information
wait for
E_NA_SR
assertion
The sequence of receiver DMA operation is illustrated in Figure 7-11.
CX82100 Home Network Processor Data Sheet
yes
RMAC issues DMA_SAVE command to DMAC to
save DMAC_{x}_Cnt1 to DMAC_{x}_Cnt3
no
RMAC collects data bits from MII as
long as the Carrier Sense is aserted.
RMAC issues DMA_XNXT to DMAC to
transfer the data to the buffer
Host programs the type of address
filtering in the E_NA_1 or E_NA_2
register (7 different types).
Host specifies the circular buffer for
the receiving channel {x} by loading
the base pointer DMAC_{x}_Ptr1
and the length DMAC_{x}_Cnt1
Host controls the receive Start/Stop
by programming the E_NA_SR bit
of the E_NA_1 or E_NA_2 register
Host initiates the Setup Frame to
configure the H/W address filtering.
Transmit & receive operations are
disabled.
RMAC interrupts the host and the
host processes the good frame
MIB counter are loaded to the
status double-word which is in
turn written to the head of the
received frame by DMAC.
RMAC resets MIB counters and
the status double-word.
A good frame received?
E_NA_SR deasserted?
A Complete frame
8 bytes of data
E_NA_SR=1?
collected?
received?
yes
yes
yes
no
yes
no
no
no
wait for
E_NA_SR
assertion
101545_038
101306C

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