cx82100 Conexant Systems, Inc., cx82100 Datasheet - Page 147

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cx82100

Manufacturer Part Number
cx82100
Description
Home Network Processor Hnp
Manufacturer
Conexant Systems, Inc.
Datasheet

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101306C
Conexant Proprietary and Confidential Information
The descriptor also contains the count of bytes to be sent in the current packet and the
logical endpoint address corresponding to that endpoint. If there is a mismatch between
the endpoint address from the buffer descriptor and the corresponding endpoint descriptor
in UDC Core, the "invalid header" status bit EPXI_INVLDHDR_INT is set and transfer
is aborted. Similar action happens if the count of bytes in the current packet is more than
64.
The firmware maintains a DMA pointer of current TX DMA packet buffer for each
endpoint. Firmware then updates the EPX_IN_TX_INC register with the number of
added data packets. APB/DMA I/F logic then transfers the data out from TX DMA buffer
into the endpoint TX FIFO buffer.
When the USB host sends a request for either bulk data or control data, then UDC
responds with the data from the TX FIFO if it has anything to transmit and continues
fetching data from TX DMA buffer if needed, or sends a NAK if data is unavailable.
When data is available, upon receiving an ACK, the status (Table 8-7) is updated with
XMIT_DONE bit and the requested logical EP_NUM number, also EPX_IN_TX_PEND
register is updated and reflecting current pending packets. The corresponding endpoint
interrupt is triggered, if enabled, and if all conditions are satisfied. If the transfer is
NAKed or an error happens during transmission, the current packet data for that endpoint
is resent.
On each consecutive NAKs from USB host, the endpoint retry counter is increased by
one. After a number of unsuccessful retries (the number programmed in the
EPXI_ERRCNT bits in U_CTR3 register), an error status bit EPXI_ERRCNT_INT is set
in the U_STAT register.
Table 8-6. Descriptor qword for Transmit (IN) Endpoint TX DMA Packet Buffer
Table 8-7. Status qword for Transmit (IN) Endpoint TX DMA Packet Buffer
Bit(s)
63:16
14:12
Bit(s)
63:24
22:20
19:16
11:8
15:0
CX82100 Home Network Processor Data Sheet
6:0
15
23
7
Default
Default
0
0
0
0
0
0
0
0
0
0
0
RDY
EP_NUM
COUNT
XMT_DONE
EP_NUM
Name
Name
Reserved.
Reserved.
Endpoint address pointer this packet transmits on.
Reserved.
Count of data bytes to be transmitted in this packet.
Reserved.
Transmission of data from current buffer complete.
Reserved.
Endpoint address pointer this packet transmits on.
Reserved.
Buffer is ready with the entire packet to be transmitted.
Description
Description
8-13

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