cx82100 Conexant Systems, Inc., cx82100 Datasheet - Page 160

• Manufacturer Part Number: cx82100
• Description: Home Network Processor Hnp
• Manufacturer: Conexant Systems, Inc.

8.8.13
8-26
Bit(s)
31
30
29
28
26
25
24
23
22
21
20
19
18
17
Type
RR
RR
RR
RR
RR
RR
RR
RR
RR
RR
RR
RR
RR
RR
USB Status Register 2 (U_STAT2: 0x00330040)
Default
1’b0
1’b0
1’b0
1’b0
1'b0
1’b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
1'b0
Conexant Proprietary and Confidential Information
If an interrupt status bit in this register is set by the UDC, the USB Interrupt bit in the
Interrupt Status Register (INT_Stat) is set if the corresponding enable bit in the U_IER2
register is set. Writing a 1 to a bit location will clear the interrupt status bit; writing a 0
has no effect.
CUR_CFG_INT
CUR_INTF_INT
EP3IN_PENDTOZERO_INT
EP2IN_PENDTOZERO_INT
EP1IN_PENDTOZERO_INT
EP0IN_PENDTOZERO_INT
EP_OUT_WATCH_INT
EP_OUT_PENDLEVEL_INT
RX_OVERRUN_INT
CFGSET_CMD_INT
INTFSET_CMD_INT
ALTSET_CMD_INT
SETUP_CMD_INT
EP3O_STALL_CLR_INT
CX82100 Home Network Processor Data Sheet
Name
Endpoint 3 Pending Register Equals 0.
Endpoint 2 Pending Register Equals 0.
Endpoint 1 Pending Register Equals 0.
Endpoint 0 Pending Register Equals 0.
Receive DMA Watchdog Timer Expired Interrupt.
Receive USB Pending Level Interrupt.
Note: The interrupt is automatically cleared when the
EP_OUT_RX_CLRPEND bit in U_CSR register is written with
a one.
Receive Overrun Interrupt.
Note: "Receiver Overrun" occurs when the RX DMA receiver
continues to receive new packet while the Receive Packet
Pending register (EP_OUT_RX_PEND) value equals the
maximum packet size (EP_OUT_RX_BUFSIZE). It is
possible that the software will write a new value to the
Receive Decrement register before handling the Overrun
Interrupt. If this happens, the H/W will proceed to update
RX_PEND as normal, but won't issue any DMA transfers as
long as the Overrun Interrupt flag is still pending.
Set Configuration Command Detected Interrupt.
Set Interface Command Detected Interrupt.
Current Configuration Detected Interrupt.
Current Interface Detected Interrupt.
ALT SET Command Detected Interrupt.
SETUP Command Detected Interrupt.
EP3_OUT Stall Clear Interrupt.
1 = The Endpoint 3 pending register (EP3_IN_TX _PEND)
1 = The Endpoint 2 pending register (EP2_IN_TX _PEND)
1 = The Endpoint 1 pending register (EP1_IN_TX _PEND)
1 = The Endpoint 0 pending register (EP0_IN_TX _PEND)
1 = All of the following conditions have occurred:
1 = The host receive buffer has received the number of
has transitioned to zero.
has transitioned to zero.
has transitioned to zero.
has transitioned to zero.
•
•
•
packets specified in the receive pending interrupt level
register (EP_OUT_PENDLEVEL).
The watchdog timer is enabled by having a
nonzero value in register USB_RXTIMER.
The receive DMA watchdog timer register counter
(USB_RXTIMERCNT) has expired (gone to zero).
The received pending register
(EP_OUT_RX_PEND) value is nonzero.
Description
101306C