cx82100 Conexant Systems, Inc., cx82100 Datasheet - Page 169

• Manufacturer Part Number: cx82100
• Description: Home Network Processor Hnp
• Manufacturer: Conexant Systems, Inc.

8.9.20
101306C
Bit(s)
14
13
12
11
10
9
8
7
6
5
4
3
Type
WO
WO
WO
WO
WO
WO
WO
RO
RO
RO
RO
RO
USB Control-Status Register (U_CSR: 0x00330088)
Default
1'b0
1'b1
1'b1
1'b1
1'b1
1'b0
1’b0
1’b0
1'b0
1'b0
1'b0
1'b0
Conexant Proprietary and Confidential Information
EP_OUT_RX_PENDISFULL
EP3_IN_TX_PENDISZERO
EP2_IN_TX_PENDISZERO
EP1_IN_TX_PENDISZERO
EP0_IN_TX_PENDISZERO
EP_OUT_RX_CLRQWCNT
EP_OUT_RX_CLRPEND
EP3_IN_TX_CLRQWCNT
EP3_IN_TX_CLRPEND
EP2_IN_TX_CLRQWCNT
EP2_IN_TX_CLRPEND
EP1_IN_TX_CLRQWCNT
CX82100 Home Network Processor Data Sheet
Name
Receive Pending Register for All OUT Endpoints Full
Status.
Transmit Pending Register for EP3_IN Zero Status.
Transmit Pending Register for EP2_IN Zero Status.
Transmit Pending Register for EP1_IN Zero Status.
Transmit Pending Register for EP0_IN is Zero Status.
Clear Receive QWCNT Register for All OUT Endpoints.
This bit self-clears one cycle after a 1 is written.
Clear Receive Pending Register for All OUT Endpoints.
This bit self-clears one cycle after a 1 is written.
Clear the Transmit QWCNT Register for EP3_IN.
This bit self-clears one cycle after a 1 is written.
Clear the Transmit Pending Register for EP3_IN.
This bit self-clears one cycle after a 1 is written.
Clear the Transmit QWCNT Register for EP2_IN.
This bit self-clears one cycle after a 1 is written.
Clear the Transmit Pending Register for EP2_IN.
This bit self-clears one cycle after a 1 is written.
Clear the Transmit QWCNT Register for EP1_IN.
This bit self-clears one cycle after a 1 is written.
0 = Receive Pending Register for all the OUT endpoints
1 = Receive Pending Register for all the OUT endpoints
0 = Transmit Pending Register for EP3_IN is nonzero.
1 = Transmit Pending Register for EP3_IN is zero.
0 = Transmit Pending Register for EP2_IN is nonzero.
1 = Transmit Pending Register for EP2_IN is zero.
0 = Transmit Pending Register for EP1_IN is nonzero.
1 = Transmit Pending Register for EP1_IN is zero.
0 = Transmit Pending Register for EP0_IN is nonzero.
1 = Transmit Pending Register for EP0_IN is zero.
0 = No effect.
1 = Clear the Receive QWCNT Register for all OUT
0 = No effect.
1 = Clear the Receive Pending Register for all OUT
0 = No effect.
1 = Clear the Transmit QWCNT Register for EP3_IN.
0 = No effect.
1 = Clear the Transmit Pending Register for EP3_IN.
0 = No effect.
1 = Clear the Transmit QWCNT Register for EP2_IN.
0 = No effect.
1 = Clear the Transmit Pending Register for EP2_IN.
0 = No effect.
1 = Clear the Transmit QWCNT Register for EP1_IN.
is not full.
is full.
endpoints.
endpoints.
Self clears
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