cx82100 Conexant Systems, Inc., cx82100 Datasheet - Page 193

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cx82100

Manufacturer Part Number
cx82100
Description
Home Network Processor Hnp
Manufacturer
Conexant Systems, Inc.
Datasheet

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10
10.1
Table 10-1. M2M Transfer Example 1
101306C
Address
Byte
0C
00
04
08
10
14
18
Source Memory
Byte-Address
to Copy: 24B
Start Source
0F0E0D0C
0B0A0908
1B1A1918
03020100
07060504
13121110
17161514
Memory to Memory Transfer Input/Output
Operation
0
Conexant Proprietary and Confidential Information
A qword buffer resides within this block to support memory to memory block transfers.
Data transfer requests are issued to the DMAC via channel 7 for reading from the source
buffer and channel 8 for writing to the destination buffer. The number of qwords to
transfer is set by M2M_Cntl. This count is big enough to initialize the entire 8 MB of
external SDRAM if desired. When M2M_Cntl is set to 0, or counts down to 0, the DMA
block transfer is done. An interrupt is set (INT_Stat:8) when the DMAC completes the
data block transfer. If M2M_DO is set, then only write transfers will occur to the
destination buffer. Since the ARM can also write to the DMA port buffer M2M_DMA, it
could use the DMAC to initialize memory to any constant.
The memory-to-memory transfer always consists of an integer number of qwords. The
source and destination addresses are always dword-aligned. Little-endian byte-
realignment is supported by using M2M_BS and using firmware for cleaning up the end
conditions. Some examples for M2M data transfers are shown in Table 10-1, Table 10-2,
and Table 10-3. The bytes highlighted in bold have to be copied or restored by firmware.
Memory before
CX82100 Home Network Processor Data Sheet
Destination
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFFFF
FFFFFFFF
Copy
M2M Data Transfer Example
0F0E0D0C
FFFFFFFF
0B0A0908
03020100
07060504
13121110
17161514
0, 00
0
M2M_Cnt = 3 qwords, DMA8_Ptr1 = 00
Destination Memory after Copy
Start Destination Byte-Address
0E0D0C0B
FFFFFF FF
0A090807
020100 xx
06050403
1211100F
16151413
1, 00
M2M_BS, DMA7_Ptr1
1
0D0C0B0A
FFFF FFFF
11100F0E
0100 xxxx
05040302
09080706
15141312
2, 00
2
0C0B0A09
FF FFFFFF
100F0E0D
00 xxxxxx
04030201
08070605
14131211
3, 00
3
10-1

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