cx82100 Conexant Systems, Inc., cx82100 Datasheet - Page 200

• Manufacturer Part Number: cx82100
• Description: Home Network Processor Hnp
• Manufacturer: Conexant Systems, Inc.

11.2.3
11.2.4
11.2.5
11-4
31:28
27:0
31:0
31:0
Bit
Bit
Bit
Type
Type
Type
WO
RW
RO
Interrupt Set Status Register (INT_SetStat: 0x00350048)
Interrupt Mask Register (INT_Msk: 0x0035004C)
Interrupt Mask Status Register (INT_Mstat: 0x00350090)
32’h00000000
32’h00000000
Default
Default
Default
4’b0
Conexant Proprietary and Confidential Information
This is a Write-Only register. The interrupt set status (INT_SetStat) register has 32 bits.
Writing a one to a bit location of this register will cause the corresponding interrupt to
occur. Writing a zero will have no effect. Only the four software interrupts defined in
INT_Stat[31:28] can be triggered by using this register.
The pending interrupts are masked (ANDed) with the interrupt mask register (INT_Msk)
before being logically ORed to the ARM interrupt input. The INT_Msk register has 32
bits. Writing a one to a bit location of this register will enable the corresponding interrupt
in INT_Stat. Writing a zero to a bit location of this register will disable the interrupt. The
enabled or active interrupts are also readable at register INT_Mstat.
This is a Read-Only register. It is logically equivalent to the AND of INT_Stat and
INT_Msk registers. It provides a convenient way for software to determine which
interrupts have occurred.
CX82100 Home Network Processor Data Sheet
Int_SetStat_x
Int_MSK_x
Int_Mstat_x
Name
Name
Name
Interrupt Set Status Control.
Reserved.
Interrupt Mask (Enable) Control.
Interrupt Mask Status.
0 = No effect.
1 = Forces an interrupt to the INTC if the corresponding bit location in
0 = Interrupts on the corresponding bit location in the INT_Stat
1 = Interrupts on the corresponding bit location in the INT_Stat
0 = Interrupts has not occurred on the corresponding bit location in
1 = Interrupts has occurred on the corresponding bit location in the
the INT_Msk register is enabled. Will cause the corresponding bit
in the INT_Stat register to be set.
register are disabled.
register are enabled.
the INT_Stat register.
INT_Stat register.
Description
Description
Description
101306C