cx82100 Conexant Systems, Inc., cx82100 Datasheet - Page 202

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cx82100

Manufacturer Part Number
cx82100
Description
Home Network Processor Hnp
Manufacturer
Conexant Systems, Inc.
Datasheet

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12.3
12-2
Timer Usage/SDRAM Refresh with Other Frequencies
Conexant Proprietary and Confidential Information
Normal HNP operation assumes BCLK is 25, 50, 62.5, 75, or 100 MHz (see Section
13.1). The timer resolution circuitry and SDRAM refresh rates are based upon these
frequencies. However, if a different frequency is desired, the resolution of the timer and
SDRAM refresh rates are based on parameter values listed in Table 12-1.
Table 12-1. Timer Resolution and SDRAM Refresh Rate
SDRAMs typically require refresh rates at approximately 15.6 µs or faster. Normal HNP
operation, when configuring BCLK as in Section 13.1, achieves a refresh rate of 12 µs.
Care must be taken to avoid use of a refresh rate that is too slow. If the refresh rate is too
fast, application performance could be reduced.
A normal example is that BCLK is programmed for 100 MHz, with PLL_B_CR_SLOW
= 0 and PLL_B_CR = 01. PCLK would then be 50 MHz, EPCLK would then be 25
MHz, and the timer resolution would be 50/50 MHz, which is equal to 1 µs. The SDRAM
refresh rate would be 100 MHz/1200, which is equal to 12 µs.
An example using a different BCLK frequency is BCLK programmed to be 80 MHz,
with PLL_B_CR_SLOW = 0 and PLL_B_CR = 01. PCLK would then be 40 MHz,
EPCLK would then be 20 MHz, and the timer resolution would be 40 MHz/50, which is
equal to 1.25 µs. The SDRAM refresh rate would be 80 MHz/1200, which is equal to
15 µs.
Another example using a different BCLK frequency is BCLK programmed to be 40
MHz, with PLL_B_CR_SLOW = 1 (default) and PLL_B_CR = 00 (default). PCLK
would then be 20 MHz, EPCLK would then be 40 MHz, and the timer resolution would
be 20 MHz/12.5 which is equal to 0.625 µs. The SDRAM refresh rate would be 40
MHz/300, which is equal to 7.5 µs.
(PLL_B_CR_SLOW)
BCLK Speed Select
CX82100 Home Network Processor Data Sheet
0 (Normal)
0 (Normal)
0 (Normal)
1 (Slow)
1 (Slow)
EPCLK Clock
(PLL_B_CR)
Rate Select
00 ( ÷ 3)
01 ( ÷ 4)
10 ( ÷ 5)
00 ( ÷ 1)
01 ( ÷ 2)
Resolution
PCLK/37.5
PCLK/62.5
PCLK/12.5
PCLK/50
PCLK/25
Refresh Rate
BCLK/1200
BCLK/1500
BCLK/900
BCLK/300
BCLK/600
SDRAM
Default at POR
Notes
101306C

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