cx82100 Conexant Systems, Inc., cx82100 Datasheet - Page 211

• Manufacturer Part Number: cx82100
• Description: Home Network Processor Hnp
• Manufacturer: Conexant Systems, Inc.

13.3
Table 13-7. PLL Register Memory Map
13.4
13.4.1
101306C
PLL_F
PLL_B
LPMR
Bit(s)
31:29
25:24
23:22
21:16
15:0
28
27
26
Register Label
Type
RW
RW
RW
RW
RW
RW
RO
PLL Register Memory Map
PLL Registers
FCLK PLL Register (PLL_F: 0x00350068)
6’b010110
16’h4DEA
(19946d)
Default
2’b00
2’b11
(22d)
1’b1
1’b1
1’b0
Conexant Proprietary and Confidential Information
PLL_F register is used by the FCLK PLL to generated the desired FCLK/UCLK.
FCLK PLL Register
BCLK PLL Register
Low Power Mode Register
PLL_F_CR_SLOW
PLL_F_LK
PLL_F_DDS
PLL_F_CR
PLL_F_PRE
PLL_F_INT
PLL_F_FRAC
CX82100 Home Network Processor Data Sheet
Name
Register Name
Reserved.
FCLK Slow Speed Select.
FCLK PLL Lock Status.
Disable FCLK ∆ ∆ ∆ ∆ Σ Σ Σ Σ Synthesizer.
USB Clock Rate Indicate.
These bits indicate to the USB interface block the rate of UCLK. For
proper USB operation, UCLK should be programmed to 48, 60, 72, or
84 MHz.
FCLK Reference Input Prescale Divider Select.
FCLK 6-bit Integer Divide Select.
FCLK 16-bit Fractional Divide.
See 13.5.
0 = Normal FCLK speed.
1 = Slow FCLK speed (one-half normal speed), FCLK = UCLK.
0 = FCLK PLL not locked.
1 = FCLK PLL locked (must be continuous 1 to indicate proper
0 = Enable FCLK ∆Σ synthesizer and select fractional divides.
1 = Disable the FCLK ∆Σ synthesizer and select integer-only
00 =
01 =
10 =
11 =
00 =
01 =
10 =
11 =
0 =
≥ 14d Enables the PLL for normal operation as a clock synthesizer.
(Default)
FCLK PLL operation).
(Default)
divides.
UCLK rate is 48 MHz. (Default)
UCLK rate is 60 MHz.
UCLK rate is 72 MHz.
UCLK rate is 84 MHz.
Reserved.
Divide by 5. (Default)
Divide by 4.
Divide by 3.
Selects PLL power-down state.
See 13.5. (Default)
0x00350068
0x0035006C
0x00350014
ASB Address
Description
RW
RW
RW
Type
0x18D04DEA
0x184E2730
0x00000000
Default Value
13.4.1
13.4.2
13.4.3
Ref.
13-5