cx82100 Conexant Systems, Inc., cx82100 Datasheet - Page 212

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cx82100

Manufacturer Part Number
cx82100
Description
Home Network Processor Hnp
Manufacturer
Conexant Systems, Inc.
Datasheet

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13.4.2
13-6
Bit(s)
31:29
25:24
23:22
21:16
15:0
28
27
26
Type
RW
RW
RW
RW
RW
RW
RO
BCLK PLL Register (PLL_B: 0x0035006C)
6’b001110
16’h2730
(10032d)
Default
2’b00
2’b01
(14d)
1’b1
1’b1
1’b0
Conexant Proprietary and Confidential Information
PLL_B register is used by the BCLK PLL to generated the desired clocks
BCLK/PCLK/EPCLK.
PLL_B_DDS
PLL_B_CR
PLL_B_CR_SLOW
PLL_B_LK
PLL_B_PRE
PLL_B_INT
PLL_B_FRAC
CX82100 Home Network Processor Data Sheet
Name
Reserved.
BCLK Slow Speed Select.
BCLK PLL Lock Status.
Disable BCLK ∆ ∆ ∆ ∆ Σ Σ Σ Σ Synthesizer.
EPCLK Clock Rate Select Divider.
For PLL_B_CR_SLOW = 0:
For PLL_B_CR_SLOW = 1:
BCLK Reference Input Prescale Divider Select.
BCLK 6-bit Integer Divide Select.
BCLK 16-bit Fractional Divide.
See 13.5.
0 = Normal BCLK speed.
1 = Slow BCLK speed (one-half normal speed). (Default)
0 = BCLK PLL not locked.
1 = BCLK PLL locked (must be continuous 1 to indicate proper
0 = Enable BCLK ∆Σ synthesizer and select fractional divides.
1 = Disable the BCLK ∆Σ synthesizer and select integer-only
00 =
01 =
10 =
00 =
01 =
10 =
00 =
01 =
10 =
11 =
0 =
≥ 14d Enables the PLL for normal operation as a clock synthesizer.
BCLK PLL operation).
(Default)
divides.
BCLK divided by 3.
BCLK divided by 4.
BCLK divided by 5.
BCLK divided by 1. (Default)
BCLK divided by 2.
Reserved.
Reserved.
Divide by 5. (Default)
Divide by 4.
Divide by 3.
Selects PLL power-down state.
See 13.5. (Default)
Description
101306C

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