cx82100 Conexant Systems, Inc., cx82100 Datasheet - Page 214

• Manufacturer Part Number: cx82100
• Description: Home Network Processor Hnp
• Manufacturer: Conexant Systems, Inc.

13.5
Table 13-8. Desired Frequencies and Programming Parameters
13-8
Example
1
2
3
4
5
6
Frequency
35.328
35.328
35.328
35.328
35.328
35.328
(MHz)
CLKI
PLL Programming
Conexant Proprietary and Confidential Information
The PLL output frequency synthesized is equal to:
where X refers to F or B for the FCLK and BCLK PLLs, respectively.
For proper operation, FCLK must always be equal or greater than BCLK.
The divide ratio for each desired clock frequency is given by:
At power-up and reset, both FCLK and BCLK and default to 48 MHz and 25 MHz,
respectively, when using a 35.328 MHz CLKI input.
Table 13-8 shows some desired frequencies and the necessary parameters for
programming the PLL_F and the PLL_B registers (assuming a 35.328 MHz input at
CLKI.
PLL
Divide
PreScaler
5
3
4
3
3
3
CX82100 Home Network Processor Data Sheet
_
Output
_
Ratio
Frequency
=
Desired
_
(MHz)
Freq
100
120
144
168
Desired
75
96
(
MHz
_
Freq
21.229620
16.304348
22.644928
20.380435
24.456522
28.532608
)
Divide
CLKI
Ratio
=
CLKI
(
MHz
PLL
_
Freq
)
_{
_
×
Freq
Integer
2
(Dec.)
X
(
×
MHz
21
16
22
20
24
28
}
PLL
_
(
PRE
MHz
)
_{
Fraction
X
)
(Dec.)
15048
19946
42266
24932
29919
34905
_ }
×
æ
ç
ç
è
PRE
PLL
_{
=
PLL
74.99998125
96.00002344
119.9999844
144.0000352
167.9999960
PLL Output
X
100.000002
Frequency
}
(MHz)
_
_{
INT
X
_ }
+
INT
PLL
+
PLL_Register
0x00D04DEA
0x00553AC8
0x02D874DF
0x03DC8859
0x0196A51A
0x01D46164
_{
PLL
X
2
101306C
}
16
_{
_
X
FRAC
2
_ }
16
FRAC
ö
÷
÷
ø
÷
2