cx82100 Conexant Systems, Inc., cx82100 Datasheet - Page 44

• Manufacturer Part Number: cx82100
• Description: Home Network Processor Hnp
• Manufacturer: Conexant Systems, Inc.

Table 2-3. CX82100 HNP Pin Signal Definitions (Continued)
2-14
MA[11:00]
MD[15:00]
MM0
MM1
MB0
MB1
MCS#
MRAS#
MCAS#
Pin Signal
B13, C12, A13,
B12, D11, C11,
F8, A11, C10,
D10, B10, A10
J14, H12, H13,
J11, H14, G13,
G12, H9, G14,
G10, F13, G11,
F14, F10, E13,
F11
E11
E10
A9
E9
C14
D13
C13
Pin No.
Conexant Proprietary and Confidential Information
CX82100 Home Network Processor Data Sheet
O
I/O
O
O
O
O
O
O
O
I/O
Ot4
Itpu/Ot4
Ot4
Ot4
Ot4
Ot4
Ot4
Ot4
Ot4
I/O Type
SDRAM/SRAM Interface
SDRAM/SRAM Address Lines. Twelve-bit multiplexed row and
column address bus addresses up to 8 MB of data.
Connect to SDRAM/SRAM A[11:0], respectively, through 51 Ω.
SDRAM/SRAM Data Lines. Sixteen-bit bidirectional data bus.
Connect to SDRAM/SRAM D[15:0], respectively, through 51 Ω.
SDRAM Input/Output Mask 0/SRAM A12.
For SDRAM interface, this signal is a mask for write access.
Connect to SDRAM I/O Mask Low input through 51 Ω.
For SRAM interface, this signal is address A12 output, Connect to
SRAM A12 input through 51 Ω.
SDRAM Input/Output Mask 1/SRAM A13.
For SDRAM interface, this signal is a mask for write access.
Connect to SDRAM I/O Mask High input through 51 Ω.
For SRAM interface, this signal is address A13 output. Connect to
SRAM A13 input through 51 Ω.
SDRAM Bank Address Select 0/SRAM A14.
For SDRAM interface, this signal selects the active bank. Connect
to SDRAM/SRAM Bank Address Select 0 input through 51 Ω for 8
MB SDRAM; leave open for 2 MB SDRAM.
For SRAM interface, this signal is address A14 output. Connect to
SRAM A14 input through 51 Ω.
SDRAM Bank Address Select 1/SRAM A15.
For SDRAM interface, this signal selects the active bank. Connect
to SDRAM/SRAM Bank Address Select 1 input through 51 Ω.
For SRAM interface, this signal is address A15 output. Connect to
SRAM A15 input through 51 Ω.
SDRAM Memory Chip Select/SRAM 2 Chip Enable.
For SDRAM interface, this active low output enables the SDRAM
command decoder. Connect to SDRAM CS# input through 51 Ω.
For SRAM interface, this active low output enables SRAM 2. If one
SRAM is used, leave open; if two SRAMs are used, connect to
SRAM 2 CE# input through 51 Ω.
SDRAM Row Address Strobe/SRAM 1 Chip Enable.
For SDRAM interface, this active low output starts SDRAM access
with strobe of row address. Connect to SDRAM RAS# input
through 51 Ω.
For SRAM interface, this active low output enables SRAM 1. If one
SRAM is used, connect to SRAM CE# input; if two SRAMs are
used, connect to SRAM 1 CE# input through 51 Ω.
SDRAM Column Address Strobe/SRAM A16.
For SDRAM interface, this active low output strobes column
address and data bytes. Connect to SDRAM CAS# input through
51 Ω.
For SRAM interface, this signal is address A16 output. Connect to
SRAM A16 input through 51 Ω.
Signal Name/Description
101306C