cx82100 Conexant Systems, Inc., cx82100 Datasheet - Page 76

• Manufacturer Part Number: cx82100
• Description: Home Network Processor Hnp
• Manufacturer: Conexant Systems, Inc.

Table 5-1. Host Master Mode Signals
5-2
HAD[15:0]
HAD[29:16]
HC[07:01]
HC08 (HRD#)
HC09 (HWR#)
HC10 (HRDY#)
HC00 (HCS0#)/GPIO32*
HAD31 (HCS4#)/GPIO31*
Notes:
* = These pins default to host functions; they can be reconfigured to GPIO pins.
Pin Signal
Conexant Proprietary and Confidential Information
The HNP Host Master Mode supports only the little-endian mode data byte orientation.
As depicted in Figure 5-2, the 32-bit little-endian ASB data bus BD[31:0] is mapped
to/from the 16-bit external host data bus HD[15:0] according to the even/odd half-word
(16 bits) data address alignment indicated by the address bit HA1.
Figure 5-2. Little-Endian Mode Data Bus Mapping
The ASB side may address the host as a slave in 16-bit or 32-bit mode. The 32-bit mode
accesses are converted to two external 16-bit accesses. The host interface is allocated 5
MB total address space. This address space is allocated to the six chip selects HCS[5:0]#
as shown in Figure 5-1 and Table 5-2.
Mode Signal
HD[15:0]
HA[20:7]
HA[6:0]
HRD#
HWR#
HRDY#
HCS0#
HCS4#
Host Master
CX82100 Home Network Processor Data Sheet
BD
even half-word address: HA1 = 0
31:24
BD[31:0] to/from ASB
N7, M9, L8, K9, J9, N10,
P10, M10, L9, K10, L10,
M11, J10, L11, N12, P12
L3, L1, M2, M1, N2, N1, M3,
N3, P3, M4, N4, P4, L4, M5
L5, M6, K6, N6, P6, L6, P7
M13
M12
P14 (CX82100-41/-42)
P14 (CX82100-11/-51/-52)
P13 (CX82100-41/-42)
J8
23:16
HD
Pin No.
15:8
15:8
7:0
7:0
Direction
Signal
I/O
O
O
O
O
O
O
BD
I
31:24
odd half-word address: HA1 = 1
Host Bus Data [15:0]
Host Bus Address [20:7]
Host Chip Select 0 (Flash ROM)
Host Bus Address [6:0]
Host Bus Read Enable
Host Bus Write Enable
Handshake for slow peripherals
Host Chip Select 4 (Spare)
BD[31:0] to/from ASB
23:16
HD
Signal Name
15:8
15:8
7:0
7:0
101306C
101545_15