cx82100 Conexant Systems, Inc., cx82100 Datasheet - Page 78

• Manufacturer Part Number: cx82100
• Description: Home Network Processor Hnp
• Manufacturer: Conexant Systems, Inc.

CX82100 Home Network Processor Data Sheet
If internal DMA timer is selected, a value must be written to HDMA_ISOC_TIMER.
This value is, in terms of BCLK periods, the time between DMA accesses to the external
peripheral. For example, when DMAing data from a peripheral to an internal destination
this register value determines the rate data is read from the peripheral.
The transfer rate is also a function of the peripheral’s data bus width. For example, if
HDMA_ISOC_TIMER is set to 200 and the peripheral is set up as an 8-bit wide device,
then 200 BCLK periods will elapse between each byte transaction with the peripheral. If
the same value is programmed, in the case of a 16-bit peripheral, the same 200 BCLK
periods will elapse between each word transaction with the peripheral. Thus, the data rate
in the case of the 16-bit peripheral is twice that of the 8-bit peripheral, even though the
HDMA_ISOC_TIMER is set to the same value in both cases.
General DMA Information
A Host-DMA transfer is configured from the ASB side via the
HDMA_SOURCE_ADDR, HDMA_DEST_ADDR, and HDMA_BCNT registers. The
Host-DMA transfer is started as soon as the HDMA_BCNT register is written to with a
nonzero value. For this reason, the HDMA_BCNT register should only be written to once
the HDMA_SOURCE_ADDR and HDMA_DEST_ADDR registers contain the
appropriate values.
DMA_SRC_ADDR_INC_DISABLE is a 1-bit field in the HST_CTRL register. When
enabled, the DMA transfer always occurs from the 24-bit address programmed into the
HDMA_SOURCE_ADDR. This is needed when a DMA transfer originates from a
register that takes its data sequentially from a FIFO.
DMA_DST_ADDR_INC_DISABLE is a 1-bit field in the HST_CTRL register. Its
purpose is similar to that of DMA_SRC_ADDR_INC_DISABLE except that it transfers
data to a static address location set in HDMA_DEST_ADDR.
HDMA_MODE_SEL is a 2-bit field in the HST_CTRL register with the MSb being the
enable for isochronous mode, and the LSb determining the variation of isochronous
mode.
The HDMA_SOURCE_ADDR register is a 24-bit register that should be written with the
address of the first byte of data to be transferred via the Host-DMA.
The HDMA_DEST_ADDR register is a 24-bit register that should be written with the
byte address of the destination for the Host-DMA data.
The HDMA_BCNT register is a 22-bit register that should be written to with the number
of bytes to be transferred after writing to the HDMA_SOURCE_ADDR and
HDMA_DEST_ADDR. Once the number of bytes has been written into the register, the
host DMA transfer begins.
The HDMA_ISOC_TIMER is an 8-bit field in the HDMA_TIMERS register that is used
when HDMA_MODE_SEL is set to 2’b10. This register is programmed with a value, in
terms of BCLK periods, equal to the length of time between consecutive external DMA
accesses.
The completion of a Host-DMA transfer is signaled by the setting of the INT_HOST
interrupt (bit 6 of INT_Stat register). This bit can be cleared by writing a 1 to the bit.
Subsequent Host-DMA transfers must not be initiated until the previous Host-DMA
transfer has been completed.
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