cx82100 Conexant Systems, Inc., cx82100 Datasheet - Page 90

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cx82100

Manufacturer Part Number
cx82100
Description
Home Network Processor Hnp
Manufacturer
Conexant Systems, Inc.
Datasheet

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5.3.10
5.3.11
5.3.12
5.3.13
5.3.14
5-16
Bit(s)
Bit(s)
31:24
Bit(s)
31:24
Bit(s)
31:22
Bit(s)
31:16
31:5
23:0
23:0
21:0
15:8
3:1
7:0
4
0
Type
Type
Type
Type
Type
RW
RW
RW
RW
RW
RW
RW
Host Master Mode Peripheral Handshake (MSTR_HANDSHAKE: 0x002D0024)
(CX82100-41/-42)
Host Master Mode DMA Source Address (HDMA_SRC_ADDR: 0x002D0028)
Host Master Mode DMA Destination Address (HDMA_DST_ADDR: 0x002D002C)
Host Master Mode DMA Byte Count (HDMA_BCNT: 0x002D0030)
Host Master Mode DMA Timers (HDMA_TIMERS: 0x002D0034)
Default
Default
Default
Default
Default
24’b0
24’b0
22’b0
1’b0
1’b0
8’b0
8’b0
Conexant Proprietary and Confidential Information
HDma_source_addr
HDma_dest_addr
HDma_byte_count
Mstr_handshake4
Mstr_handshake0
HDMA_ISOC_TIMER
HDMA_INACTIVE_TIMER
CX82100 Home Network Processor Data Sheet
Name
Name
Name
Name
Name
Reserved.
HCS4 HRDY# Handshake Enable.
Reserved.
HRDY# Polarity.
Reserved.
Least significant 24 bits of the address of the first byte of DMA source
data.
Reserved.
Least significant 24 bits of the first location of the DMA destination.
Reserved.
The number of bytes of data to be transferred via the host DMA.
0 = Disable HRDY# handshake.
1 = Enable HRDY# handshake.
0 = Active low
1 = Active high
Reserved.
Timer which dictates the transfer rate for an isochronous mode
DMA transfer in terms of the number of BCLK periods.
The minimum interval, in terms of number of BCLK periods,
between subsequent accesses to an external DMA source or
destination.
Description
Description
Description
Description
Description
101306C

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