cx82100 Conexant Systems, Inc., cx82100 Datasheet - Page 96
cx82100
Manufacturer Part Number
cx82100
Description
Home Network Processor Hnp
Manufacturer
Conexant Systems, Inc.
Datasheet
1.CX82100.pdf
(226 pages)
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6.10
Figure 6-2. EMC Clocking Interface
Figure 6-3. EMC I/O Timing
6-6
M CLK
BCLK
MODULE
CLKGEN
M D
M A
HNP
Notes:
A = tck-q + tdsm + tpo
B = tasu
C = clock skew = tdi + tdsm + tpo
D = ta
E = tsu + tpi + tdsm
F = (clk period / 2) - tdi - tdsm - tpo
EMC I/O Clock Interface and Timing
BCLK
Conexant Proprietary and Confidential Information
The EMC I/O clock interface is illustrated in Figure 6-2.
The EMC I/O timing is illustrated in Figure 6-3.
asb_sdram
BCLK
CX82100 Home Network Processor Data Sheet
A
ADDR
Q
D
B
scan m ux
scan mux
scan mux
W here:
MCLK
MA
MD
PAD
PAD
PAD
tck-q = asb_sdram flop clk-q delay
tsu = asb_sdram flop setup tim e
th = asb_sdram flop hold tim e
tdsm = HNP scan m ux delay
tpo = output pad delay
tpi = input pad delay
tdi = HNP inverter delay
ta = sdram read access tim e
C
MD
MA
MCLK
D
ext_sdram
D
Q
DATA
101545_026
E
101545_027
F
101306C
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