alc262w-vd2-gr Realtek Semiconductor Corporation, alc262w-vd2-gr Datasheet
alc262w-vd2-gr
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alc262w-vd2-gr Summary of contents
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... ALC262-GR ALC262-VB Series (ALC262-VB0-GR, ALC262SRS-GR, ALC262H-GR) ALC262-VC Series (ALC262-VC1-GR, ALC262-VC2-GR) ALC262-VD Series (ALC262-VD2-GR, ALC262W-VD2-GR) 4-CHANNEL DAC AND 6-CHANNEL ADC HIGH DEFINITION AUDIO CODEC DATASHEET Realtek Semiconductor Corp. No. 2, Innovation Road II, Hsinchu Science Park, Hsinchu 300, Taiwan Tel.: +886-3-578-0211. Fax: +886-3-577-6047 www ...
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... This document could include technical inaccuracies or typographical errors. TRADEMARKS Realtek is a trademark of Realtek Semiconductor Corporation. Other names mentioned in this document are trademarks/registered trademarks of their respective owners. USING THIS DOCUMENT This document is intended for the hardware and software engineer’s general information on the Realtek ALC262 Series Audio Codecs ...
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... Meets Intel low power ECR compliant and power status control for all analog converter and pin widgets. See section 7.5 Power Management, page 28. 1.9 2008/04/15 Added information for all ALC262 series (version A/B/C/D). Added part number ALC262W-VD2-GR in section 12 Ordering Information, page 78. 4-Ch DAC and 6-Ch ADC High Definition Audio Code nd SPDIF output: iii ...
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GENERAL DESCRIPTION ..............................................................................................................................................1 2. FEATURES .........................................................................................................................................................................3 2. ARDWARE EATURES 2. ..................................................................................................................................................4 OFTWARE EATURES 3. SYSTEM APPLICATIONS...............................................................................................................................................5 4. BLOCK DIAGRAM ...........................................................................................................................................................6 4.1. ALC262 A/B V ERSION 4.2. ALC262 C V ....................................................................................................................................................7 ERSION 4.3. ALC262 D V ...
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SUPPORTED VERBS AND PARAMETERS................................................................................................................31 8.1. V – ERB ET ARAMETERS 8.1.1. Parameter – Vendor ID (Verb ID=F00h, Parameter ID=00h)............................................................................31 8.1.2. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h)..........................................................................32 8.1.3. Parameter – Subordinate Node Count (Verb ID=F00h, Parameter ...
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V – ERB UNCTION ESET 8.39. V – ERB ET IGITAL 8.40. V – ERB ET IGITAL ONVERTER 8.41 OLUME NOB 8.42 ...
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I/O P ........................................................................................................................................................13 ABLE IGITAL INS I/O P .......................................................................................................................................................13 ABLE NALOG INS ....................................................................................................................................................14 ABLE ILTER EFERENCE .........................................................................................................................................................14 ABLE OWER ROUND ABLE ...
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T 53. V – ABLE ERB ET ONVERTER T 54. V – ABLE ERB ET IN IDGET T 55. V – ABLE ERB ET IN IDGET T 56. V – ...
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– ALC262 A/B V IGURE LOCK IAGRAM – ALC262 C V IGURE LOCK IAGRAM – ALC262 D V IGURE LOCK IAGRAM IGURE NALOG ...
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General Description The ALC262 series are 4-Channel DAC and 6-Channel ADC High Definition Audio Codecs with UAA (Universal Audio Architecture). Featuring two 24-bit stereo DACs and three 24-bit stereo ADCs (the ALC262, ALC262-VB and ALC262-VC support 20-bit ADC format, ...
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Two functions are added in the ALC262 C version: • Addition of a digital microphone interface. The ALC262 C version supports most digital microphones currently available. With digital microphone implementation, a notebook computer can achieve better voice input quality without ...
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Features 2.1. Hardware Features High-performance DACs with 100dB SNR ADCs with 90dB SNR (A-weighting) Meets WLP (Windows Logo Program) 3.10 and future WLP requirements that become effective from 01 June 2008 Two stereo DACs support 16/20/24-bit PCM for stereo ...
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Supports both analog DC volume control and GPI digital volume control (requires driver support) 4 GPIOs (General Purpose Input/Output) for customized applications Optional EAPD (External Amplifier Power Down) is supported Power support: Digital: 3.3V; Analog: 3.3V/5.0V Power management and enhanced ...
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Microphone Acoustic Echo Cancellation (AEC), Noise Suppression (NS), and Beam Forming (BF) technology for voice application Smart multiple streaming operation HDMI audio driver for AMD platform ® Dolby PCEE program™ (optional software feature) ® SRS TrueSurround HD (optional software feature) ...
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Block Diagram 4.1. ALC262 A/B Version Figure 1. 4-Ch DAC and 6-Ch ADC High Definition Audio Code Block Diagram – ALC262 A/B Version 6 ALC262 Series Datasheet Track ID: JATR-1076-21 Rev. 1.9 ...
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ALC262 C Version Note: The ALC262 C Version supports digital MIC (DMIC-CLK, DMIC-DATA). 4-Ch DAC and 6-Ch ADC High Definition Audio Code Figure 2. Block Diagram – ALC262 C Version 7 ALC262 Series Datasheet Track ID: JATR-1076-21 Rev. 1.9 ...
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ALC262 D Version Note: The ALC262 D Version supports digital MIC (DMIC-CLK, DMIC-DATA) and S/DPIF-OUT2. 4-Ch DAC and 6-Ch ADC High Definition Audio Code Figure 3. Block Diagram – ALC262 D Version 8 ALC262 Series Datasheet Track ID: JATR-1076-21 ...
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Analog Input/Output Unit Pin Complex widgets NID=14h~16h, 18h~1Bh are re-tasking IO. Output_Signal_Left Output_Signal_Right Input_Signal_Left Input_Signal_Right 4-Ch DAC and 6-Ch ADC High Definition Audio Code A R EN_OBUF EN_AMP R EN_OBUF EN_IBUF Figure 4. Analog Input/Output Unit 9 ALC262 Series ...
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Pin Assignments 5.1. ALC262 A/B Version Note: C and D versions (Figure 6, page 11, and Figure 7, page 12) support digital MIC (pin 2, 46) and Scalable I/O Power (pin 9). Figure 5. 5.2. Green Package and Version ...
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ALC262 C Version The C version supports digital MIC (pin 2, 46) and Scalable I/O Power (pin 9). 5.4. Green Package and Version Identification Green package is indicated by a ‘G’ in the location marked ‘T’ in Figure 6. ...
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ALC262 D Version The D version supports digital MIC (pin 2, 46), Scalable I/O Power (pin 9), and S/PDIFO2 (pin45). 5.6. Green Package and Version Identification Green package is indicated by a ‘G’ in the location marked ‘T’ in ...
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Pin Descriptions 6.1. Digital I/O Pins Name Type Pin No. Description RESET SYNC I 10 BITCLK I 6 SDATA-OUT I 5 SDATA- SPDIFI / IO 47 EAPD SPDIFO SPDIFO2 O 45 GPIO0 ...
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Name Type Pin No. Description MIC1 LINE1 LINE1 PCBEEP I 12 LINE-OUT LINE-OUT HP-OUT HP-OUT MONO-OUT O 37 Sense Sense ...
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High Definition Audio Link Protocol 7.1. Link Signals The High Definition Audio (HDA) Link is the digital serial interface that connects the HDA codecs to the HDA Controller. The HDA link protocol is controller synchronous, based on a 24.0MHz ...
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Signal Definitions Item Description BCLK 24.0MHz of bit clock sourced from the HDA controller and connecting to all codecs. SYNC 48kHz of signal is used to synchronize input and output streams on the link sourced from the ...
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Signaling Topology The HDA controller supports two SDOs for the outbound stream SDIs for the inbound stream. RST#, BCLK, SYNC, SDO0, and SDO1 are driven by controller to codecs. Each codec drives its own point-to-point SDI ...
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Frame Composition 7.2.1. Outbound Frame – Single SDO An outbound frame is composed of one 32-bit command stream and multiple data streams. There are one or multiple sample blocks in a data stream. Only one sample block exists in ...
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Outbound Frame – Multiple SDO The HDA controller allows two SDO signals to be used to stripe outbound data, completing transmission in less time to get more bandwidth. If software determines the target codec supports multiple SDO capability, it ...
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Inbound Frame – Single SDI An Inbound Frame – A single SDI is composed of one 36-bit response stream and multiple data streams. Except for the initialization sequence (turnaround and address frame), SDI is driven by the codec at ...
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Inbound Frame – Multiple SDI A codec can deliver data to the controller on multiple SDIs to achieve higher bandwidth inbound stream exceeds the data transfer limits of a single SDI, the codec can divide the data ...
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The cadence ‘12-11-11-12-11-11-12-11-11-12-11-11-11- (repeat)’ interleaves 13 frames containing no sample blocks in every 160 frames. It provides a low long-term frequency drift for 44.1kHz of delivery rate. Rates in sub-multiples (1/n) of 44.1kHz also follow this cadence and interleave n ...
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Table 9. Rate Delivery Cadence 11.025kHz {12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{11}{-} (repeat) 22.05kHz {12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{12}{-}{11}{-}{11}{-}{11}{-} (repeat) 44.1kHz 12-11-11-12-11-11-12-11-11-12-11-11-11- (repeat 88.2kHz 12 -11 -11 -12 - 174.4kHz 12 -11 -11 -12 -11 11.025kHz: {12}=YNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNN {11}=YNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNNYNNN { - }=NNNN ...
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Reset and Initialization There are two types of reset within an HDA link: • Link Reset. Generated by assertion of the RST# signal, all codecs return to their power on state • Codec Reset. Generated by software directing a ...
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Exit from ‘Link Reset’: If BCLK is re-started for any reason (codec wake-up event, power management, etc.) Software is responsible for de-asserting RST# after a minimum of 100µsec BCLK running time (the 100µsec provides time for the codec PLL to ...
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Codec Initialization Sequence The codec drives SDI high at the last bit of SYNC to request a Codec Address (CAD) from the controller. The codec will stop driving the SDI during this turnaround period. The controller drives SDI to ...
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Verb and Response Format 7.4.1. Command Verb Format There are two types of verbs: one with 4-bit identifiers (4-bit verbs) and 16-bits of data, the other with 12-bit identifiers (12-bit verbs) and 8-bits of data. Table 10 shows the ...
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Power Management 7.5.1. ALC262 A/B/C Versions The ALC262 does not support Wake-Up events when in low power mode. All power management state changes in widgets are driven by software. Table 14 shows the System Power State Definitions. In the ...
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ALC262 Version A/B/C Powered Down Conditions Table 16. ALC262 Version A/B/C Powered Down Conditions Condition LINK Response powered down LOUT DAC powered down LINE ADC powered down MIX ADC powered down Headphone Driver powered down Mixers powered down Reference ...
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All power management state changes in widgets are driven by software. Table 17 indicates the definitions of power states. In the ALC262-VD, the Audio Function (NID=01h), input converter, output converter, and each pin widget supports power control. Software may have ...
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ALC262 Version D Powered Down Conditions Table 18. ALC262 Version D Powered Down Conditions Condition LINK Response powered down LOUT DAC powered down LINE ADC powered down MIX ADC powered down Headphone Driver powered down All headphone drivers are ...
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Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h) Table 21. Parameter – Revision ID (Verb ID=F00h, Parameter ID=02h) Codec Response Format Bit Description 31:24 Reserved. Read as 0’s. 23:20 MajRev. The major version number (in decimal) of the HDA ...
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Parameter – Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h) Table 24. Parameter – Audio Function Capabilities (Verb ID=F00h, Parameter ID=08h) Codec Response Format Bit Description 31:17 Reserved. Read as 0’s. 16 Beep Generator. A ‘1’ indicates the presence of ...
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Parameter – Supported PCM Size, Rates (Verb ID=F00h, Parameter ID=0Ah) Parameter in audio function provides default information about formats. Individual converters have their own parameters to provide supported formats if their ‘Format Override’ bit is set. Table 26. Parameter ...
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Parameter – Supported Stream Formats (Verb ID=F00h, Parameter ID=0Bh) Parameters in this node only provide default information for audio function groups. Individual converters have their own parameters to provide supported formats if the ‘Format Override’ bit is set. Table ...
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Parameter – Amplifier Capabilities (Verb ID=F00h, Input Amplifier Parameter ID=0Dh) Parameters in this node provide audio function group default information. Individual converters have their own parameters to provide amplifier capabilities if the ‘AMP Param Override’ bit is set. Table ...
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Parameter – Connect List Length (Verb ID=F00h, Parameter ID=0Eh) Parameters in this node provide audio function widget connection information. Table 31. Parameter – Connect List Length (Verb ID=F00h, Parameter ID=0Eh) Codec Response Format Bit Description 31:8 Reserved. Read as ...
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Parameter – Supported Power States (Verb ID=F00h, Parameter ID=0Fh) (ALC262 D Version) The ALC262 version D is designed to meet Intel’s low-power-state white paper and is ECR HDA-015B compliant. Table 33. Parameter – Supported Power States (Verb ID=F00h, Parameter ...
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Parameter – GPIO Capabilities (Verb ID=F00h, Parameter ID=11h) Table 35. Parameter – GPIO Capabilities (Verb ID=F00h, Parameter ID=11h) Codec Response Format Bit Description 31 GPIWake=0. The ALC262 does not support GPIO wake up function. 30 GPIUnsol=1. The ALC262 supports ...
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Verb – Get Connection Select Control (Verb ID=F01h) Table 37. Verb – Get Connection Select Control (Verb ID=F01h) Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Verb ID=F01h Codec Response for Analog Port-A/B/C/D/E/F Bit Description 31:8 0’s. ...
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Verb – Set Connection Select (Verb ID=701h) Table 38. Verb – Set Connection Select (Verb ID=701h) Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Verb ID=701h 8.4. Verb – Get Connection List Entry (Verb ID=F02h) Table 39. ...
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Codec Response for NID=0Bh (Mixer) Bit Description 31:24 Connection List Entry (N+3). Returns 1Bh (Pin Complex - LINE2) for N=0~3. 23:16 Connection List Entry (N+2). Returns 1Ah (Pin Complex - LINE1) for N=0~3. 15:8 Connection List Entry (N+1). Returns 19h ...
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Codec Response for NID =14h~15h, 18h~1Bh (PORT-A ~ PORT-F) Bit Description 31:24 Connection List Entry (N+3). Returns 00h. 23:16 Connection List Entry (N+2). Returns 00h. 15:8 Connection List Entry (N+1). Returns 0Dh (Sum Widget NID=0Dh) for N=0~3. Returns 00h for ...
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Codec Response for NID=22h/23h/24h (Sum Widget before MIX/LINE/MIC ADCs) Bit Description 31:24 Connection List Entry (N+3). Returns 1Bh (Pin Complex - LINE2) for N=0~3. Returns 15h (Pin Complex-SURR) for N=4~7. 23:16 Connection List Entry (N+2). Returns 1Ah (Pin Complex - ...
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Verb – Get Coefficient Index (Verb ID=Dh) Table 42. Verb – Get Coefficient Index (Verb ID=Dh) Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Codec Response for NID=20h (Realtek Defined Hidden Registers) Bit Description 31:16 Reserved. Read ...
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Verb – Set Processing Coefficient (Verb ID=4h) Table 45. Verb – Set Processing Coefficient (Verb ID=4h) Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Codec Response for All NID Bit Description 31:0 0’s. 8.11. Verb – Get ...
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Codec Response for NID=0Bh (MIXER Sum Widget) Bit Description 31:8 0’s. 7 Bit- ‘Get Amplifier Gain’: Input Amplifier Mute. 0: Unmute 1: Mute (Default for all Index). Bit- ‘Get Amplifier Gain’: Read as 0 ...
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Verb – Set Amplifier Gain (Verb ID=3h) This verb is used to set amplifier gain/attenuation in each widget. Table 47. Verb – Set Amplifier Gain (Verb ID=3h) Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh ‘Set’ Payload ...
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Verb – Get Converter Format (Verb ID=Ah) Table 48. Verb – Get Converter Format (Verb ID=Ah) Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Codec Response for NID=02h, 03h, 06h (Output Converters: LINE-OUT DAC, HP-OUT DAC, S/PDIF-OUT). ...
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Verb – Set Converter Format (Verb ID=2h) Table 49. Verb – Set Converter Format (Verb ID=2h) Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh ‘Set’ Payload in Command Bit[15:0] Bit Description 31:16 Reserved. Read ...
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Verb – Get Power State (Verb ID=F05h) (ALC262 A/B/C Version) Table 50. Verb – Get Power State (Verb ID=F05h) (ALC262 A/B/C Version) Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Codec Response for NID=01h (Audio Function Group) ...
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Verb – Get Power State (Verb ID=F05h) (ALC262 D Version) Table 51. Verb – Get Power State (Verb ID=F05h) (ALC262 D Version) Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Codec Response for NID=01h (Audio Function Group) ...
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Verb – Set Power State (Verb ID=705h) Table 52. Verb – Set Power State (Verb ID=705h) Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Verb ID=705h ‘Power State’ in Command Bit[7:0] Bit Description 7:6 Reserved. Read as ...
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Verb – Set Converter Stream, Channel (Verb ID=706h) Table 53. Verb – Set Converter Stream, Channel (Verb ID=706h) Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Verb ID=706h ‘Stream and Channel’ in Command Bit[7:0] Bit Description 31:8 ...
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Verb – Set Pin Widget Control (Verb ID=707h) Table 55. Verb – Set Pin Widget Control (Verb ID=707h) Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Verb ID=707h ‘Pin Control’ in command [7:0]: (NID=14h, 15h, 16h, 18h~1Bh) ...
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Verb – Set Unsolicited Response Control (Verb ID=708h) Enable a widget to generate an unsolicited response. Table 57. Verb – Set Unsolicited Response Control (Verb ID=708h) Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Verb ID=708h ‘EnableUnsol’ ...
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Verb – Execute Pin Sense (Verb ID=709h) Table 59. Verb – Execute Pin Sense (Verb ID=709h) Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Verb ID=709h ‘Payload’ in Command Bit[7:0] Bit Description 7:1 Reserved. Read as 0’s. 0 ...
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Verb – Set Configuration Default Bytes (Verb ID=71Ch/71Dh/71Eh/71Fh for Bytes The BIOS can use this verb to figure out the default conditions for the Pin Widgets 14h~1Bh and 1Eh~1Fh such as ...
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Verb – Set BEEP Generator (Verb ID=70Ah) Table 63. Verb – Set BEEP Generator (Verb ID=70Ah) Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Verb ID=71Bh ‘Divider’ in Set Command Bit Description 31:8 Reserved. 7:0 Frequency Divider, ...
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Verb – Set GPIO Data (Verb ID=715h) Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Verb ID=715h ‘Data’ in Set command for NID=01h (Audio Function Group) Bit Description 31:4 Reserved. 3:0 GPIO[3:0] Output Data. The value written ...
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Verb – Set GPIO Enable Mask (Verb ID=716h) Table 67. Verb – Set GPIO Enable Mask (Verb ID=716h) Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Verb ID=716h Codec Response for NID=01h (Audio Function Group) Bit Description ...
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Verb – Set GPIO Direction (Verb ID=717h) Table 69. Verb – Set GPIO Direction (Verb ID=717h) Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Verb ID=717h Codec Response for NID=01h (Audio Function Group) Bit Description 31:4 Reserved. ...
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Verb – Set GPIO Unsolicited Response Enable Mask (Verb ID=719h) Table 71. Verb – Set GPIO Unsolicited Response Enable Mask (Verb ID=719h) Set Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Verb ID=719h Codec Response for NID=01h (Audio ...
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Verb – Get Digital Converter Control 1 & Control 2 (Verb ID=F0Dh, F0Eh) Table 73. Verb – Get Digital Converter Control 1 & Control 2 (Verb ID=F0Dh, F0Eh) Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Verb ...
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Verb – Set Digital Converter Control 1 & Control 2 (Verb ID=70Dh, 70Eh) Table 74. Verb – Set Digital Converter Control 1 & Control 2 (Verb ID=70Dh, 70Eh) Set Command Format (Verb ID=70Xh, Set Control 1) Bit [31:28] Bit ...
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Get/Set Volume Knob Widget (NID=21h) (Verb ID=F0Fh/70Fh) Table 75. Get/Set Volume Knob Widget (NID=21h) (Verb ID=F0Fh/70Fh) Get Command Format Bit [31:28] Bit [27:20] CAd=X Node ID=Xh Verb ID=F0Fh Codec Response for NID=21h (Volume Knob Widget) Bit Description 31:8 Reserved. ...
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Electrical Characteristics 9.1. DC Characteristics 9.1.1. Absolute Maximum Ratings Parameter Power Supplies Digital Power for Core Digital Power for Link (C, D)* Analog Power Ambient Operating Temperature Storage Temperature Pin 33 (DCVOL) (ver. A/B/C) All Pins (ver ...
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Digital Filter Characteristics Filter Symbol ADC Lowpass Filter Passband (A/B silicon) Passband (C/D silicon) Stopband Stopband Rejection Passband Ripple (A/B) Passband Ripple (C/D) DAC Lowpass Filter Passband (A/B silicon) Passband (C/D silicon) Stopband Stopband Rejection Passband Ripple (A/B) Passband ...
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AC Characteristics 9.2.1. Link Reset and Initialization Timing Parameter RESET# Active Low Pulse Width RESET# Inactive to BCLK Startup Delay for PLL Ready Time SDI Initialization Request 4 BCLK BCLK SYNC SDO SDI RESET# 4-Ch DAC and 6-Ch ADC ...
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Link Timing Parameters at the Codec Table 82. Link Timing Parameters at the Codec Parameter BCLK Frequency BCLK Period BCLK Jitter BCLK High Pulse Width BCLK Low Pulse Width SDO Setup Time at Both Rising and Falling Edge of ...
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S/PDIF Output and Input Timing Parameter *1 S/PDIF-OUT Frequency *1 S/PDIF-OUT Period S/PDIF-OUT Jitter *1 S/PDIF-OUT High Level Width *1 S/PDIF-OUT Low Level Width S/PDIF-OUT Rising Time S/PDIF-OUT Falling Time *2 S/PDIF-IN Period S/PDIF-IN Jitter *2 S/PDIF-IN High Level ...
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Analog Performance Standard Test Conditions Parameter Full Scale Input Voltage All Inputs (Gain=0dB) All ADC Full Scale Output Voltage All DAC (Ver. A/B/C) All DAC (Ver. D) S/N (A Weighted) ADC DAC THD+N ADC DAC Headphone Out @32Ω Load ...
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Application Notes 10.1. Application Circuit Please contact Realtek for the latest application circuits. To get the best compatibility in hardware design and software driver, any modification should be confirmed by Realtek. Realtek may upload the latest application circuits onto ...
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Volume Control Via GPIO0/GPIO1 Detected low pulses generated at GPIO0 and GPIO1 are used to calculate the Up and Down count into 7 bits of volume steps. ‘Mute’ is also sampled to toggle the mute status. Hardware will not ...
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The ALC262 supports a two-wire interface for the digital microphone and operates in single channel (mono type) or stereo channels (stereo) digital microphone mode. One pin is clock output to the digital microphone, and the other is a serial pin. ...
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Mechanical Dimensions See the Mechanical Dimensions notes on the next page. 4-Ch DAC and 6-Ch ADC High Definition Audio Code Track ID: JATR-1076-21 ALC262 Series Datasheet Rev. 1.9 ...
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Mechanical Dimensions Notes SYMBOL MILLIMETER MIN TYP 0. 1.35 1. 9.00 BSC D1 7.00 BSC D2 5.50 E 9.00 BSC E1 7.00 BSC E2 5.50 b 0.17 0.20 e ...
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... Version C2 silicon, LQFP-48 &‘Green’ package ALC262-VD2-GR Version D2 silicon, LQFP-48 &‘Green’ package ALC262W-VD2-GR ALC262-VD2-GR + Waves MaxxAudio (software feature) Note 1: See section 5 Pin Assignments, page 10 for Green package and version identification. Note 2: Above parts are tested under AVDD =5.0V. If customers have lower AVDD request, please contact Realtek sales representatives or agents ...