hd66765 Renesas Electronics Corporation., hd66765 Datasheet
hd66765
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hd66765 Summary of contents
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... RAM. The HD66765 and HD66764 have various functions for reducing the power consumption of an LCD system. The HD66765 has a low-voltage operation (1.8 V min.) and an internal RAM to display a maximum of 132RGB-by-176-dot color, and the HD66764 has a step-up circuit to generate the LCD- drive voltage, a bleeder resistor for the drive interface with the LCD, and voltage-followers ...
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... Maximum 132RGB-by-176-dot display in combination with the HD66764 common driver Internal RAM capacity: 34,848 bytes 396-segment liquid crystal display driver n-raster-row AC liquid-crystal drive (C-pattern waveform drive) Internal oscillation and hardware reset Shift change of segment driver Type Number Type Number HD66765TB0 HCD66765BP External Appearance Bending TCP Au-bump chip 2 ...
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... HD66765 Block Diagram Vcc Index register (IR) IM2- IM0/ID CS* System interface bits - 8 bits E/WR*/SCL - Serial peripheral (SPI) RW/RD* 16 DB0/SDI, DB1/SDO, to DB15 16 CCS* Common driver CCL interface (serial) CDA RESET* TEST OSC1 OSC2 CPG Control register (CR) Address counter Timing generator (AC) 12 Bit operation ...
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... HD66765 HD66765 PAD Arrangement - Chip size : 13.22mm x 3.85mm - Chip thickness : 550um (typ.) - PAD coordinate : PAD center - Coordinate origine : Chip center - Au bump size : (1) 80um DUMMY1, DUMMY2-DUMMY39, DUMMY40, DUMMY41, DUMMY42 (2) 35um x 80um SEG304-SEG93 (3) 80um x 35um SEG386-SEG321, SEG76-SEG11 (4) 45um x 80um SEG10-SEG1, SEG396-SEG387, SEG320-SEG305, SEG92-SEG77 - Au bump pitch : Refer PAD coordinate - Au bump height : 15um (typ ...
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... HD66765 PAD Coordinate No. PAD Name X Y No. PAD Name X 1 DUMMY1 -6480 -1795 101 DUMMY29 4522 -1795 2 SEG10 -6234 -1795 102 DUMMY30 4623 -1795 3 SEG9 -6174 -1795 103 DUMMY31 4723 -1795 4 SEG8 -6113 -1795 104 DUMMY32 4823 -1795 5 SEG7 -6053 -1795 105 DUMMY33 ...
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... When a serial interface is selected, the IM0 pin is used as the ID setting for a device code. Selects the HD66765: Low: HD66765 is selected and can be accessed High: HD66765 is not selected and cannot be accessed Must be fixed at GND level when not in use. Selects the register. Low: Index/status ...
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... Low: the HD66764 is selected and can receive a serial transfer. High: the HD66764 is not selected and cannot receive a serial transfer. Input for the LCD-drive voltage for the segment driver, which can be provided by the HD66764’s on-chip power supply. VSH 4 1 3.6 V; GND (logic HD66765 ...
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... HD66765 Table 1 Pin Functional Description (cont) Number of Signals Pins I/O Connected to OSC1 Oscillation- OSC2 resistor RESET MPU or external R-C circuit VccDUM O Input pins GNDDUM O Input pins Dummy — — TEST 1 I GND Functions Connect an external resistor for R-C oscillation. When providing clocks from outside, open OSC2. ...
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... Serial Peripheral Interface port). The interface mode is selected by the IM2-0 pins. The HD66765 has three 16-bit registers: an index register (IR), a write data register (WDR), and a read data register (RDR). The IR stores index information from the control registers and the GRAM. The WDR temporarily stores data to be written into control registers and the GRAM, and the RDR temporarily stores data read from the GRAM ...
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... HD66765 Bit Operation The HD66765 supports the following functions: a write data mask function that selects and writes data into the GRAM in bit units, and a logic operation function that performs logic operations or conditional determination on the display data set in the GRAM and writes into the GRAM. With the 16-bit bus interface, these functions can greatly reduce the processing loads of the MPU graphics software and can rewrite the display data in the GRAM at high speed ...
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... A serial interface circuit provides an interface with the HD66764 common driver. When sending an instruction setting from the HD66765 to a common driver, a register setting value from within the HD66765 is transferred via the serial interface circuit. A transfer is started by setting a serial transfer enable in the HD66765. However, transfer to and reading from the common driver are not possible during standby ...
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... HD66765 Table Relationship between GRAM address and display position (SGS=0) SEG/COM pins CMS=0 CMS COM1 COM176 "0000"H COM2 COM175 "0100"H COM3 COM174 "0200"H COM4 COM173 "0300"H COM5 COM172 "0400"H COM6 COM171 "0500"H COM7 COM170 "0600"H COM8 COM169 "0700"H COM9 COM168 " ...
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... palette SEG (395-3n Lower 6-bits address (0 to 131) 13 HD66765 "0000"H "0100"H "0200"H "0300"H "0400"H "0500"H "0600"H "0700"H "0800"H "0900"H "0A00"H "0B00"H "0C00"H "0D00"H "0E00"H "0F00"H "1000"H " ...
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... The internal operation of the HD66765 is determined by signals sent from the microcomputer. These signals, which include the register selection signal (RS), the read/write signal (R/W), and the data bus signals (DB15 to DB0), make up the HD66765 instructions. There are nine categories of instructions that: • ...
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... DB14 DB13 DB12 Status Read The status read instruction reads the internal status of the HD66765. L7–0: Indicate the driving raster-row position where the liquid crystal display is being driven. C6–0: Read the contrast setting values (CT6–0). R/W RS DB15 DB14 DB13 DB12 R ...
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... NL4–0: Specify the LCD drive duty ratio. The duty ratio can be adjusted for every eight raster-rows. GRAM address mapping does not depend on the setting value of the drive duty ratio. DB11 DB10 DB9 DB8 DB7 DB6 DB5 0 0 CMS SGS HD66765 DB4 DB3 DB2 DB1 DB0 NL4 NL3 NL2 NL1 NL0 ...
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... Duty 396 x 152 dots 1/152 Duty 396 x 160 dots 1/160 Duty 396 x 168 dots 1/168 Duty 396 x 176 dots 1/176 Duty 17 HD66765 Common Driver Used Setting disabled COM1–COM16 COM1–COM24 COM1–COM32 COM1–COM40 COM1–COM48 COM1–COM56 COM1–COM64 COM1– ...
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... NW5 DB11 DB10 DB9 DB8 DB7 DB6 DB5 BT3 BT2 BT1 BT0 0 DC2 DC1 HD66765 DB4 DB3 DB2 DB1 DB0 NW4 NW3 NW2 NW1 NW0 DB4 DB3 DB2 DB1 DB0 DC0 AP1 AP0 SLP STB 0 0 VC2 ...
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... VC2-0: Sets an adjustment factor for the Vci voltage (VC2-0). SLP: When SLP = 1, the HD66765 enters the sleep mode, where the internal display operations are halted except for the R-C oscillator, thus reducing current consumption. Only the following instructions can be executed during the sleep mode. Power control (BS2– ...
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... CP11 Figure 8 Entry Mode and Compare Register Instruction The write data sent from the microcomputer is modified in the HD66765 and written to the GRAM. The display data in the GRAM can be quickly rewritten to reduce the load of the microcomputer software processing. For details, see the Graphics Operation Function section. ...
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... Compare operaion (with compare register) LG2-0 = "100" Replacement of matched readdata LG2-0 = "101" Replacement of unmatched read data LG2-0 = "110" Replacement of matched write data LG2-0 = "111" Replacement of ummatched write data Write data mask (WM11-0) GRAM 21 HD66765 I/D1-0 = "11" Horizontal: increment Vertical: increment 0000h AF83 AF83h 0000h ...
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... SEG/COM pin outputs set to the GND level. Because of this, the HD66765 can control the charging current for the LCD with AC driving. When D1–0 = 01, the internal display of the HD66765 is performed although the display is off. When D1-0 = 00, the internal display operation halts and the display is off. ...
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... IDX2-0 setting at the time of transfer selects the instruction for the common driver as listed below. To change an instruction setting on the common driver, first change the instruction bit on the HD66765, select the instruction, which includes the changed instruction bit, from the list below, by setting IDX2-0 as required ...
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... Change the instruction bit setting Instruction setting change corresponding to the HD66765 Transfer to the common driver must be executed immediately after setting up the instruction Index set R0Ah Instruction read (During transfer "0" YES (Transfer can be executed) Specify the IDX2 the HD66764 ...
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... R-C oscillation frequency DB11 DB10 DB9 DB8 DB7 DB6 DB5 0 0 DIV1 DIV0 Clock Cycles per Raster-row fosc / 1 fosc / 2 fosc / 4 fosc / 8 25 HD66765 DB4 DB3 DB2 DB1 DB0 0 RTN3 RTN2 RTN1 RTN0 ...
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... DB5 VL22 VL21 VL20 VL17 VL16 VL15 VL22 VL21 VL20 VL12 VL11 VL10 Display-start Raster-row 1st raster-row 2nd raster-row 3rd raster-row : : : : 175th raster-row 176th raster-row 26 HD66765 [Hz] DB4 DB3 DB2 DB1 DB0 VL14 VL13 VL12 VL11 VL10 ...
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... SE17–10 SS27–20 SE27–20 4FH. For details, see the Screen-division Driving Function section. DB11 DB10 DB9 DB8 DB7 DB6 DB5 SE12 SE11 SE10 SS17 SS16 SS15 SE22 SE21 SE20 SS27 SS26 SS25 27 HD66765 DB4 DB3 DB2 DB1 DB0 SS14 SS13 SS12 SS11 SS10 SS24 SS23 SS22 SS21 SS20 ...
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... HEA0 HSA7 HSA6 HSA5 VEA2 VEA1 VEA0 VSA7 VSA6 VSA5 HEA Window address setting range "00"h HSA7-0 "00"h VSA7-0 AF83h 28 HD66765 DB4 DB3 DB2 DB1 DB0 HSA4 HSA3 HSA2 HSA1 HSA0 VSA4 VSA3 VSA2 VSA1 VSA0 AFh. HEA7-0 "83"h VEA7-0 " ...
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... DB11 DB10 DB9 DB8 DB7 DB6 DB5 HD66765 DB4 DB3 DB2 DB1 DB0 DB4 DB3 DB2 DB1 DB0 ...
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... PK82 PK81 PK93 PK92 PK91 PK103 PK102 PK101 PK113 PK112 PK111 PK123 PK122 PK121 PK133 PK132 PK131 PK143 PK142 PK141 PK153 PK152 PK151 30 HD66765 DB4 DB3 DB2 DB1 DB0 DB4 DB3 DB2 DB1 DB0 ...
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... GRAM address setting is latched from the GRAM to the internal read-data latch. The data on the data bus (DB11–0) becomes invalid and the second-word read is normal. When bit processing, such as a logical operation, is performed within the HD66765, only one read can be processed since the latched data in the first word is used. ...
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... PK113 PK112 PK111 PK110 PK104 PK133 PK132 PK131 PK130 PK124 PK153 PK152 PK151 PK150 PK144 32 HD66765 DB4 DB3 DB2 DB1 DB0 PK04 PK03 PK02 PK01 PK00 PK24 PK23 PK22 PK21 PK20 PK44 PK43 PK42 PK41 PK40 PK64 PK63 PK62 ...
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Table 17 Instruction List Reg. No. Register Name R/W RS DB15 DB14 DB13 DB12 DB11 DB10 IR Index Status read R00h Start oscillation Device code read 1 ...
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... The HD66765 is internally initialized by RESET input. Reset the common driver as its settings are not automatically reinitialized when the HD66765 is reset. The reset input must be held for at least 1 ms. Do not access the GRAM or initially set the instructions until the R-C oscillation frequency is stable after power has been supplied (10 ms) ...
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... Figure 27 Interface to 8-bit Microcomputer Note: Transfer synchronization function for an 8-bit bus interface The HD66765 supports the transfer synchronization function which resets the upper/lower counter to count upper/lower 8-bit data transfer in the 8-bit bus interface. Noise causing transfer mismatch between the eight upper and lower bits can be corrected by a reset triggered by consecutively writing a 00H instruction four times ...
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... RS R/W E "00"H Upper or DB15-DB8 Lower (1) Figure 28 8-bit Transfer Synchronization "00"H "00"H "00"H Upper (2) (3) (4) 8-bit transfer syhchronization 36 HD66765 Lower ...
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... ID pin. The five upper bits must be 01110. Two different chip addresses must be assigned to a single HD66765 because the seventh bit of the start byte is used as a register select bit (RS): that is, when data can be written to the index register or status can be read, and when instruction can be issued or data can be written to or read from RAM ...
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... Dummy (Output) read 1 read 2 Start Note: Five bytes of the RAM read data after the start byte are invalid. The HD66765 starts to read the correct RAM data from the sixth byte. Figure 29 Procedure for Transfer on Clock-Synchronized Serial Bus Interface ...
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... SDO Dummy read 1 (Output) Start Note: One byte of the read data after the start byte are invalid. The HD66765 starts to read the correct data from the second byte. Figure 29 Procedure for Transfer on Clock-Synchronized Serial Bus Interface (cont) Status read: Status read: ...
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... HD66765 High-Speed Burst RAM Write Function The HD66765 has a high-speed burst RAM-write function that can be used to write data to RAM in one- fourth the access time required for an equivalent standard RAM-write operation. This function is especially suitable for applications which require the high-speed rewriting of the display data, for example, display of color animations, etc ...
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... Cannot be used Can be used Can be used ID0 bit=0: Set the lower two bits to 11 ID0 bit=1: Set the lower two bits to 00 Cannot be used Dummy write operations may have to be inserted according to a window address- range specification Can be set by word 41 HD66765 ...
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... HD66765 High-Speed RAM Write in the Window Address When a window address range is specified, RAM data which optional window area can be rewritten consecutively and quickly by inserting dummy write operations so that RAM access counts become 4N as shown in the tables below. Dummy write operations may have to be inserted as the first or last operations for a row of data, depending on the horizontal window-address range specification bits (HSA1 to 0, HEA1 to 0) ...
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... Figure 32 Example of the High-Speed RAM Write with a Window Address-Range Specification "0000"h GRAM address map "8012"h Window address-range specification (rewrite area) Window address-range setting HSA = "12"h, HEA = "30"h VSA = "80"h, VEA = "A0"h 152 43 HD66765 "A030"h "A083"h ...
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... HD66765 Window Address Function When data is written to the on-chip GRAM, a window address-range which is specified by the horizontal address register (start: HSA7-0, end: HEA7-0) or the vertical address register (start: VSA7-0, end: VEA7-0) can be written to consecutively. Data is written to addresses in the direction specified by the AM bit (increment/decrement). When image data, etc ...
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... Window address-range specification area HSA7-0 = "10"H, HSE7-0 = "2F"H VSA7-0 = "20"H, VEA7-0 = "5F"H Figure 33 Example of Address Operation in the Window Address Specification "0083"H "202F"H "212F"H "5F2F"H "AF83"H I/D = "1" (increment "0" (horizontal writing) 45 HD66765 ...
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... HD66765 Graphics Operation Function The HD66765 can greatly reduce the load of the microcomputer graphics software processing through the 16-bit bus architecture and internal graphics-bit operation function. This function supports the following write data mask function that selectively rewrites some of the bits in the 12-bit write data. ...
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... Write bit mask 16 Graphics RAM (GRAM) Figure 34 Data Processing Flow of the Graphics Operation Microcomputer 16 Write-data latch 12 3 Logical operation bit 12 Compare bit (CP11— Write-mask register 47 HD66765 (LG2—0) (WM11—0) ...
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... HD66765 Write-data Mask Function The HD66765 has a bit-wise write-data mask function that controls writing the two-byte data from the microcomputer to the GRAM. Bits that are 0 in the write-data mask register (WM11–0) cause the corresponding DB bit to be written to the GRAM. Bits that are 1 prevent writing to the corresponding GRAM bit to the GRAM ...
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... Logical/Compare Operation Function The HD66765 performs a logical operation or conditional replacement between the two-byte write data sent from the microcomputer and the read data from the GRAM. The logical operation function has four types: replacement, OR, AND, and EOR. The conditional replacement performs a compare operation for the set value of the compare register (CP11– ...
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... HD66765 Graphics Operation Processing 1. Write mode LG2–0 = 000 This mode is used when the data is horizontally written at high speed. It can also be used to initialize the graphics RAM (GRAM draw borders. The write-data mask function (WM11–0) is also enabled in these operations. After writing, the address counter (AC) automatically increments decrements by 1 (I/D = 0), and automatically jumps to the counter edge one-raster-row below after it has reached the left or right edge of the GRAM ...
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... Note: 1. The bits in the GRAM indicated by ’*’ are not changed. 2. After writin to address "AF00"H, the AC jumps to "0001"H. Figure 37 Writing Operation of Write Mode 2 DB0 DB0 Write data (1) Write data (2) Write data (3) GRAM 51 HD66765 ...
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... HD66765 3. Write mode LG2–0 = 110/111 This mode is used when the data is horizontally written by comparing the write data and the set value of the compare register (CP11–0). When the result of the comparison in a byte unit satisfies the condition, the write data sent from the microcomputer is written to the GRAM. In this operation, the write-data mask function (WM11– ...
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... Figure 39 Writing Operation of Write Mode 4 DB0 DB0 Conditional Compare replacement operaton Conditional Compare replacement operaton Write data (1) GRAM 53 HD66765 ...
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... HD66765 5. Read/Write mode LG2–0 = 001/010/011 This mode is used when the data is horizontally written at high speed by performing a logical operation with the original data. It reads the display data (original data), which has already been written in the GRAM, performs a logical operation with the write data sent from the microcomputer, and rewrites the data to the GRAM ...
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... Note: 1. The bits in the GRAM indicated by ’*’ are not changed. 2. After writin to address "AF00"H, the AC jumps to "0001"H. Figure 41 Writing Operation of Read/Write Mode 2 DB0 DB0 Logical operation (OR Logical operation (OR Read data (1) + Write data (1) Read data (2) + Write data (2) GRAM 55 HD66765 ...
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... HD66765 7. Read/Write mode LG2–0 = 100/101 This mode is used when the data is horizontally written by comparing the original data and the set value of compare register (CP11–0). It reads the display data (original data), which has already been written in the GRAM, compares the original data and the set value of the compare register in byte units, and writes the data sent from the microcomputer to the GRAM only when the result of the comparison satisfies the condition ...
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... Note: 1. The bits in the GRAM indicated by ’*’ are not changed. 2. After writin to address "AF00"H, the AC jumps to "0001"H. Figure 43 Writing Operation of Read/Write Mode 4 DB0 DB0 Compare operaton C Conditional replacement Compare operaton C Conditional replacement Write data (1) Write data (2) GRAM 57 HD66765 ...
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... HD66765 Grayscale Palette The HD66765 incorporates a grayscale palette to simultaneously display 4,096 out of 13,824 possible colors. The grayscales consist of sixteen five-bit palettes. The 24-stage grayscale levels can be selected from the five-bit palette data. In this palette, a pulse-width control system (PWM) is used to eliminate flicker in the LCD display. The time over which the LCDs are switched on is adjusted according to the level and grayscales are displayed so that flicker is reduced and grayscales are clearly displayed ...
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... Notes: 1. The unlit level corresponds to a black display when a normally-black color-LCD panel is used, and a white display when a normally-white color-LCD panel is used. 2. The all-lit level corresponds to a white display when a normally-black color-LCD panel is used, and a black display when a normally-white color-LCD panel is used HD66765 ...
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... Signals to set instructions for CR oscillation, the display timing signal, and the common driver are supplied from the HD66765 to the common driver. The LCD drive voltage is generated by the common driver. The LCD segment drive level (VSH) is also supplied from the common driver. On/off control of the display is required to be controlled by both the common and segment driver ...
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... The HD66765 serial interface circuit is only for transmitting, and cannot be used for receiving data from the common driver. Serial transfer is started by setting the serial transfer register (TE) in the HD66765 to 1. After TE has been set to 1, CDA will be output in synchronization with CCS*, CCL, and CCL. Transfer is in 16-bit blocks ...
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... HD66765 c) Serial Transfer Sequence Change the instruction bit setting Instruction setting change corresponding to the HD66765 Transfer to the common driver must be executed immediately after setting up the instruction Index set R0Ah Instruction read (During transfer "0" YES (Transfer can be executed) Specify the IDX2 the common side ...
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... Standby set (STB = "1") Oscillation start Standby Sleep cancel (SLP = "0") Wait 10 ms cancel Power setting Display on flow 63 HD66765 [Sleep] Display off flow Sleep set Sleep set (SLP = "1") Serial transfer Sleep cancel Serial transfer Power setting flow ...
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... When using the HD66765 with the HD66764 common driver, the relationship between the SEG and COM output levels is as shown in the following figure. The LCD drive level (VSH, VSL) which is used by the HD66765 is supplied from the HD66764 common driver. While the display is off, SEG and COM outputs go to GND level. ...
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... Frame-Frequency Adjustment Function The HD66765 has an on-chip frame-frequency adjustment function. The frame frequency can be adjusted by the instruction setting (DIV, RTN) during the LCD drive as the oscillation frequency is always same. When the display duty is changed, the frame frequency can be adjusted to be the same. ...
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... HD66765 Example Calculation 1 To set the maximum frame frequency Display duty: 1/176 Retrace-line period: 0 clock (RTN3 0000) Operation clock division ratio: 1 division fosc = 25) clock 1 division 176 lines = 264 (kHz) In this case, the CR oscillation frequency becomes 264 kHz. The external resistance value of the CR oscillator must be adjusted to be 264 kHz ...
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... Reversed AC Drive The HD66765 supports not only the LCD reversed AC drive in a one-frame unit (B-pattern waveform) but also the n-raster-row reversed AC drive which alternates in an n-raster-row unit from one to 64 raster- rows (C-pattern waveform). When a problem affecting display quality occurs, such as crosstalk at high- duty driving of more than 1/64 duty, the n-raster-row reversed AC drive (C-pattern waveform) can improve the quality ...
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... HD66765 Screen-division Driving Function The HD66765 can select and drive two screens at any position with the screen-driving position registers (R14h and R15h). Any two screens required for display are selectively driven and a duty ratio is lowered by LCD-driving duty setting (NL4-0), thus reducing LCD-driving voltage and power consumption. ...
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... The following restrictions must be satisfied when setting the start line (SS17-10) and end line (SE17-10) of the 1st screen driving position register (R14) and the start line (SS27-20) and end line (SE27-20) of the 2nd screen driving position register (R15) for the HD66765. Note that incorrect display may occur if the restrictions are not satisfied. ...
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... Modification history Revision 0.1 First release - HD66765 ...
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... HD66765 When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All right reserved: No one is permitted to reproduce or duplicated, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document ...