hd66766r Renesas Electronics Corporation., hd66766r Datasheet
hd66766r
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hd66766r Summary of contents
Page 1
... STN colors. A 16-bit high-speed bus interface and high-speed RAM write function enable efficient data transfer and high-speed rewriting of data to the graphics RAM. The HD66766R has various functions for reducing the power consumption of a LCD system, such as low-voltage operation of 2.2 V/min., a step-up circuit to generate a maximum of 12-times the LCD drive voltage from the supplied voltage, and voltage-followers to decrease the direct current flow in the LCD drive bleeder-resistors ...
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... HD66766R Various color-display control functions - 65K out of 140K possible colors can be displayed at the same time (grayscale palette incorporated) - Vertical scroll display function in raster-row units - Partial LCD drive of two screens in any position Low-power operation supports: - Vcc = 2.2 to 3.6 V (low-voltage) - Common driving voltage = Segment driving voltage = VOUT power voltage = 4 ...
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... HD66766R HD66766R PAD Arrangement (Straight Output Arrangement) Chip size: 18.65mm×2.63mm Chip thickness: 400um (typ.) Pad coordinate: Pad center Coordinate origin: Chip center Au bump size: ( × DUMMY1 DUMMY2 RESET1*~ RESET3*, DUMMY10, DUMMY11 DUMMY12 DUMMY13 ( × 140 m COM1 ~ COM176 ...
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... HD66766R Table 2 HD66766R PAD Coordinate (Straight)(No.1) No. pad name X Y No. pad name X 1 DUMMY1 -9193 -1168 81 OSC1 1284 -1168 2 DUMMY2 -8835 -1168 82 GNDDUM8 1440 -1168 3 RESET1* -8678 -1168 83 IM2 1597 -1168 4 CEP -8498 -1168 84 VCCDUM1 1754 -1168 5 CEP -8398 -1168 85 IM1 1910 -1168 ...
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... HD66766R Table 2 cont. HD66766R PAD Coordinate • traight• No.2) No. pad name X Y No. pad name X 401 SEG230 1216 1145 481 SEG150 -1862 1145 402 SEG229 1178 1145 482 SEG149 -1900 1145 403 SEG228 1140 1145 483 SEG148 -1938 1145 404 SEG227 ...
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... HD66766R HD66766R PAD Arrangement (LacedOutput Arrangement) Chip size: 18.65mm×2.63mm Chip thickness: 400 m (typ.) Pad coordinate: Pad center Coordinate origin: Chip center (1) 80 m×80 m DUMMY1, DUMMY2, RESET1*~ RESET3*, DUMMY10, DUMMY11 DUMMY12, DUMMY13 (2) 38 m×63 m COM1~COM176 SEG1~SEG396 Au bump pitch: Refer to pad coordinate Au bump hight: 15 m(typ ...
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... HD66766R Table 3 HD66766R PAD Coordinate (Laced)(No.1) No. pad nameX Y No. pad nameX 1DUMMY1 -9193 -1168 81 OSC1 1284 -1168161 COM32 9108 -411 241 SEG390 7296 1098321 SEG31042561098 2DUMMY2 -8835 -1168 82 GNDDUM8 1440 -1168162 COM34 9201 -373 242 SEG389 7258 1191322 SEG30942181191 3RESET1* -8678 -1168 83 IM2 ...
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... HD66766R Table 3 cont. HD66766R PAD Coordinate (Laced•j(No.2) No. pad nameX Y No. pad nameX 401 SEG230 12161098481 SEG150 -18621098561 SEG70 -4902 1098641 COM155 - 7980 1191 402 SEG229 11781191482 SEG149 -19001191562 SEG69 -4940 1191642 COM153 - 8018 1098 403 SEG228 11401098483 SEG148 -19381098563 SEG68 -4978 1098643 COM151 - 8056 1191 ...
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... Rev. 1.0-1 / September 2002 Control Register (CR) Address Counter ( Bit Operation Write data 64 Read data latch latch 48 16 Graphic RAM (GRAM) 46,464 bytes Timinig generator Figure 3 HD66766R Block Diagram Description 9 Palette Register (RK, GK, BK) VSL PWM Grayscale Circuit SEG1 to SEG396 Common COM1 to driver COM176 ...
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... When a serial interface is selected, the IM0 pin is used as the ID setting for a device code. Selects the HD66766R: Low: HD66766R is selected and can be accessed High: HD66766R is not selected and cannot be accessed Must be fixed at GND level when not in use. Selects the register. Low: Index/status ...
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... HD66766R Table 4 cont. Number of Signals Pins I/O Connected to DB2-DB15 14 I/O MPU SEG1– 396 O LCD SEG396 COM1– 176 O LCD COM176 VCH, VCL 2 — Capacitor for stabilization, shot key barrier diode or external power supply VM 1 — Capacitor for stabilization or external power supply VSH 1 — ...
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... HD66766R Table 4 cont. Number of Signals Pins I/O Connected to C12+, C12- 2 — Step-up capacitance C21+, C21- 2 — Step-up capacitance C22+, C22- 2 — Step-up capacitance C23+, C23- 2 — Step-up capacitance C24+, C24- 2 — Step-up capacitance CEP, CEM 2 — Step-up capacitance or open VREFL 1 — VCC or external ...
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... Clock synchronized serial interface. The IM2-0 pins select the interface mode. The HD66766R has three 16-bit registers: an index register (IR), a write data register (WDR), and a read data register (RDR). The IR stores index information from the control registers and the GRAM. The WDR temporarily stores data to be written into control registers and the GRAM, and the RDR temporarily stores data read from the GRAM ...
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... Oscillation Circuit (OSC) The HD66766R can provide R-C oscillation simply through the addition of an external oscillation-resistor between the OSC1 and OSC2 pins. The appropriate oscillation frequency for operating voltage, display size, and frame frequency can be obtained by adjusting the external-resistor value. Clock pulses can also be supplied externally ...
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... HD66766R GRAM ADDRESS DIAGRAM (HD66766R) Table 7 Relationship between GRAM address and display position (SGS = “0”) SEG/COM pins CMS=0 CMS COM1 "0001"H COM176 "0000"H COM2 COM175 "0100"H "0101"H COM3 COM174 "0200"H "0201"H COM4 "0301"H COM173 "0300"H "0401"H COM5 COM172 " ...
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... HD66766R Table 9 Relationship between GRAM address and display position (SGS = “1”) SEG/COM pins CMS CMS COM176 COM1 "0083"H "0082"H "0183"H "0182"H COM2 COM175 "0283"H "0282"H COM3 COM174 COM4 COM173 "0383"H "0382"H COM172 COM5 "0483"H "0482"H "0583"H " ...
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... The internal operation of the HD66766R is determined by signals sent from the microcomputer. These signals, which include the register selection signal (RS), the read/write signal (R/W), and the data bus signals (DB15 to DB0), make up the HD66766R instructions. There are eight categories of instructions that: ...
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... DB11 Figure 4 Index Instruction Status Read: SR The status read instruction reads the internal status of the HD66766R. L7–0: Indicate the driving raster-row position where the liquid crystal display is being driven. C6–0: Read the contrast setting values (CT6-0) RS R/W DB15 DB14 DB13 DB12 ...
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... HD66766R Driver Output Control (R01h) R/W RS DB15 DB14 DB13 DB12 Figure 7 CMS: Selects the output shift direction of a common driver. When CMS = 0, COM1 shifts to COM176. When CMS = 1, COM176 shifts to COM1. SGS: Selects the output shift direction of the segment driver. When SGS = 0, data are output SEG1 to SEG396. When SGS = 1, data are output SEG396 to SEG1. When SGS = 0, SEG1 pin assigns the color display to < ...
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... HD66766R Table 11 NL Bits and Drive Duty NL4 NL3 NL2 NL1 NL0 Display Size 396 x 8 dots 396 x 16 dots 396 x 24 dots 396 x 32 dots 396 x 40 dots ...
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... HD66766R LCD-Driving-Waveform Control (R02h) R/W RS DB15 DB14 DB13 DB12 Figure 8 LCD-Driving-Waveform Control Instruction B/C: When B B-pattern waveform is generated and alternates in every frame for LCD drive. When B C-pattern waveform is generated and alternates in each raster-row specified by bits EOR and NW4–NW0 in the LCD-driving-waveform control register. For details, see the n-raster-row Reversed AC Drive section ...
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... VC2-0: Set an adjustment factor for the Vci1 voltage (VC2-0). SLP: When SLP = 1, the HD66766R enters the sleep mode, where the internal display operations are halted except for the R-C oscillator, thus reducing current consumption. Only the following instructions can be executed during the sleep mode. Power control (BS2– ...
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... HD66766R Table 12 Display bias setting table Determine the LCD drive bias according to its display duty, and select combination of boosting ratio of the step-up circuit 2 and bias amplifier ratio so as not to exceed voltage control of Vci2 and VCH. See the LCD Voltage Generation Circuit regarding how to determine the LCD drive bias, VCH voltage and contrast adjustment for the following settings ...
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... HD66766R Table 13 Display bias setting table VC2 VC1 VC0 Vci1 control range 0.92 x Vcc 0.87 x Vcc 0.83 x Vcc 0.8 x Vcc 0.76 x Vcc 0.73 x Vcc 0.68 x Vcc Vci1 control amplifier suspends. (Vci1 can be supplied externally.) ...
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... HD66766R Table 16 Operating clock frequency of the Booster 1 and 2 Operating clock frequency in DC2 DC1 DC0 the booster 32-divided clock 64-divided clock 32-divided clock 64-divided clock 32-divided clock 64-divided clock 32-divided clock 64-divided clock ...
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... HD66766R VR2–0: These bits amplifies 1.1 to 3.4 times the VREFL as output voltage VREFM of LCD drive reference voltage generation circuit. The VREFM should be smaller than VOUT level. Table 19 Contrast control VR2 VR1 VR0 VREFM voltage VREFL x 1 VREFL x 1 VREFL x 1.4 ...
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... Entry Mode (R05h ) Compare resister (R06h) The write data sent from the microcomputer is modified in the HD66766R and written to the GRAM. The display data in the GRAM can be quickly rewritten to reduce the load of the microcomputer software processing. For detail, see the Graphics Operation Function section. ...
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... HD66766R LG2-0: Compare the data read from the GRAM by the microcomputer with the compare resisters (CP15 compare/logical operation and writes the results to GRAM. For details, see the Logical/Compare Operation Function. CP15-0: Set the compare resister for the compare operation with the data read from the GRAM or written by the microcomputer ...
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... D1–0: Display is on when D1 = “1” and off when When off, the display data remains in the GRAM, and can be displayed instantly by setting D1 = “1”. When D1 is “0”, the display is off with all of the SEG/COM pin outputs set to the GND level. Because of this, the HD66766R can control the charging current for the LCD with AC driving. ...
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... HD66766R Frame Cycle Control (R0Bh) R/W RS DB15 DB14 DB13 DB12 DB11 RTN3-0: Set the line retrace period (RTN3- added to raster-row cycles. becomes long according to the number of clocks set at RTN3-0. DIV1-0: Set the division ratio of clocks for internal operation (DIV1-0). ...
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... HD66766R Vertical Scroll Control (R11h) R/W RS DB15 DB14 DB13 DB12 DB11 W 1 VL27 VL26 VL25 VL24 VL23 Figure 16 Vertical Scroll Control Instruction VL17-10: Specify the display-start raster-row at the 1 th raster-row from the first to 176 can be selected. restarts from the first raster-row. The display-start raster-row (VL17-10) is valid only when VLE1 = “1”. ...
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... HD66766R st 1 Screen Driving Position (R14h Screen Driving Position (R15h) R/W RS DB15 DB14 DB13 DB12 SE16 SE15 SE14 SE13 W 1 SE17 W SE27 SE26 SE25 SE24 SE23 1 SS17–0: Specify the driving start position for the first screen in a line unit. The LCD driving starts from the 'set value + 1' common driver. SE17– ...
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... HD66766R HSA 0000h VSA Window Address VEA GRAM Address space Figure 19 Window Address Setting Range Note: 1. Ensure that the window address area is within the GRAM address space high-speed write mode, data are written to GRAM in four-words. Thus, dummy write operations should be inserted depending on the window address area ...
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... HD66766R GRAM address setting is not allowed in the standby mode. Ensure that the address is set within the specified window address. Table 24 GRAM Address Range AD15 to AD0 GRAM Setting "0000"H to “0083"H Bitmap data for COM1 "0100"H to "0183"H Bitmap data for COM2 "0200”H to "0283"H Bitmap data for COM3 " ...
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... HD66766R Table 25 GRAM data setting ...
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... Write (data of address N) Second words DB11-0 = > GRAM Automatic address update: N+ Dummy read (invalid data) First word GRAM => Read data latch Write (data of address N) Second words ii) Logical operation processing in the HD66766R 36 DB4 DB3 DB2 DB1 DB0 Sets the I/D, AM, HSA/HSE, VSA/VEA Address: N set Dummy read (invalid data) GRAM => ...
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... HD66766R Gray Scale Palette Control (R30h to R3Fh) Table 26 Grayscale Palette Control Instruction R/W RS DB15 DB14 DB13 DB12 PK R30 R31 R32 R33 R34 ...
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... HD66766R Instruction List (HD66766R) Table 27 Upper Code Reg. Register No. Name Index Status read R00h Start oscillation Device code read R01h Driver ...
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... HD66766R Instruction List (cont.) Upper Code Reg. Register R/ RS No. Name R21h RAM 0 1 AD15–8 (upper) address set R22 RAM data 0 1 Write data (upper) write RAM data 1 1 Read data (upper) read R30h Grayscale ...
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... The HD66766R is internally initialized by RESET input. Reset the gate driver/Power supply IC as its settings are not automatically reinitialized when the HD66766R is reset. The reset input must be held for at least 200 ms. Do not access the GRAM or initially set the instructions until the R-C oscillation frequency is stable after power has been supplied (10 ms) ...
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... HD66766R Parallel Data Transfer 16-bit Bus Interface Setting the IM2/1/0 (interface mode) to the “GND”/“GND”/“GND” level allows 68-system E-clock- synchronized 16-bit parallel data transfer. Setting the IM2/1/0 to the “GND”/”Vcc”/”GND” level allows 80-system 16-bit parallel data transfer. When the number of buses or the mounting area is limited, use an 8-bit bus interface ...
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... HD66766R Note: Transfer synchronization function for an 8-bit bus interface The HD66766R supports the transfer synchronization function which resets the upper/lower counter to count upper/lower 8-bit data transfer in the 8-bit bus interface. Noise causing transfer mismatch between the eight upper and lower bits can be corrected by a reset triggered by consecutively writing a “ ...
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... ID pin. The five upper bits must be “01110”. Two different chip addresses must be assigned to a single HD66766R because the seventh bit of the start byte is used as a register select bit (RS): that is, when RS = “0”, data can be written to the index register or status can be read, and when RS = “ ...
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... HD66766R a) Timing of basic data-transfer through clock synchronized serial interface Transfer start CS* (input SDI "0" "1" "1" "1" "0" (input) Device code Start byte ...
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... HD66766R C) Transfer data read from GRAM CS* (input) SCL (input) Start byte SDI RS="1" (input) R/W="1" Dummy SDO Dummy read (1) read (2) (output) "Start" Five bytes invalid dummy data are read after start byte. 6th data is valid from GRAM. Figure 31 Procedure for transfer through the clock synchronized serial interface (c) ...
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... When the high-speed RAM-write mode (HWM) is selected, data for writing to RAM is once stored to the HD66766R internal register. When data is selected four times per word, all data is written to the on-chip RAM. While this is taking place, the next data can be written to an internal register so that high-speed and consecutive RAM writing can be executed for animated displays, etc ...
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... HD66766R Note the following when using high-speed RAM write mode. Notes: 1. The logical and compare operation cannot be used. 2. Data is written to RAM each four words. address must be set to the following values. *When I/D0=0, the lower two bits in the address must be set to “11” and be written to RAM. ...
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... HD66766R High-Speed RAM Write in the Window Address When a window address range is specified, RAM data which optional window area can be rewritten consecutively and quickly by inserting dummy write operations so that RAM access counts become 4N as shown in the tables below. Dummy write operations may have to be inserted as the first or last operations for a row of data, depending on the horizontal window-address range specification bits (HSA1 to 0, HEA1 to 0) ...
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... HD66766R An example of high-speed RAM write with a window address-range specified is shown below. The window address-range can be rewritten to consecutively and quickly by inserting two dummy writes at the start of a row and three dummy writes at the end of a row, as determined by using the window address-range specification bits (HSA1 to 0 “10”, HEA1 to 0 “00”). ...
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... HD66766R Window Address Function When data is written to the on-chip GRAM, a window address-range which is specified by the horizontal address register (start: HSA7-0, end: HEA7-0) or the vertical address register (start: VSA7-0, end: VEA7- 0) can be written to consecutively. Data is written to addresses in the direction specified by the AM bit (increment/decrement). When image data, etc ...
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... HD66766R Graphic Operation Function The HD66766R can greatly reduce the load of the microcomputer graphics software processing through the 16-bit bus architecture and internal graphics-bit operation function. This function supports the following write data mask function that selectively rewrites some of the bits in the 16-bit write data. ...
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... HD66766R Write-data Mask Function The HD66766R has a bit-wise write-data mask function that controls writing the 16-bit data from the microcomputer to the GRAM. Bits that are “0” in the write-data mask register (WM15–0) cause the corresponding DB bit to be written to the GRAM. Bits that are “1” prevent writing to the corresponding GRAM bit to the GRAM ...
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... HD66766R Graphics Operation Processing 1. Write mode LG2-0 = “000” This mode is used when the data is horizontally written at high speed. It can also be used to initialize the graphics RAM ( GRAM ) or to draw borders. The write-data mask function ( WM15-0 ) are also enabled in these operations. After writing, the address counter ( AC ) automatically increments I decrements I and automatically jumps to the counter edge one-raster below after it has reached the left or right edge of the GRAM ...
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... HD66766R 2. Write mode LG2-0 = “000” This mode is used when the data is vertically written at high speed. It can also be used to initialize the GRAM, develop the font pattern in the vertical direction, or draw borders. The write-data mask function ( WM15-0 ) are also enabled in these operations. After writing, the address counter ( AC ) automatically increments by 256, and automatically jumps to the upper-right edge ( I upper- left egde ( I following the I/D bit after it has reached the lower edge of the GRAM ...
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... HD66766R 3. Write mode LG2-0 = 110/111 This mode is used when the data is holizontally written by comparing the write data and the set value of the compare resister ( CP7-0 ). When the result of the comparison in a byte unit satisfies the condition write-data mask function ( WM15-0 ) are also enabled. After writing , the address counter ( AC ) automatically increments I decrements I and automatically jumps to the counter edge one-raster-raw below after it has reached the left or right edge of the GRAM ...
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... HD66766R 4. Write mode LG2-0 = 110/111 This mode is used when a vertical comparison is performed between the write data and the set value of the compare resister ( CP15 write the data . When the result by the comparison in a byte unit satisfies the condition, the write data sent from the microcomputer is written to the GRAM. In this operation, write data mask function ( WM15-0 ) are also enabled ...
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... HD66766R 4096 colors Display Function HD66766R is equipped with 4096 colors display function. When setting SPR bit = 1, it operates 4096 color display function, and uses 16 bits instead of 12 bits. Upper 4 bits are invalid when operating 4096 colors display function. While operating 4096 colors display function, write mode 3 and 4 in graphic operation are not usable ...
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... HD66766R Grayscale Palette The HD66766R incorporates a grayscale palette to simultaneously display 65K of the 140,608 possible colors. The grayscales consist of 32 6-bit palettes. The 52-stage grayscale levels can be selected from the 6-bit palette data. For the display data, the four-bit data in the GRAM written from the microcomputer is used. ...
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... HD66766R Grayscale Palette Table The grayscale register that is set for each palette register (PK) can be set to any level. 52-grayscale lighting levels can be set according to palette values (“000000” to “110100”). Table 35 Grayscale Control Level Palette Register Value (PK ...
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... HD66766R Notes: 1. The unlit level corresponds to a black display when a normally-black color-LCD panel is used, and a white display when a normally-white color-LCD panel is used ...
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... HD66766R RGB pixel data and Grayscale level Table 36 G pixel data and output level G pixel data Output level 000000 PK0 000001 (PK0+PK1)/2 000010 PK1 000011 (PK1+PK2)/2 000100 PK2 000101 (PK2+PK3)/2 000110 PK3 0000111 (PK3+PK4)/2 001000 PK4 001001 (PK4+PK5)/2 001010 PK5 001011 ...
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... HD66766R Table pixel data and output level R, B pixel data Output level 00000 PK0 00001 PK1 00010 PK2 00011 PK3 00100 PK4 00101 PK5 00110 PK6 00111 PK7 01000 PK8 01001 PK9 01010 PK10 01011 PK11 01100 PK12 01101 PK13 ...
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... Setting flow for low power consumption instruction Sleep Mode Setting the sleep mode bit (SLP) to “1” puts the HD66766R in the sleep mode, where the device stops all internal display operations, thus reducing current consumption. Specifically, LCD operation is completely halted. Here, all the SEG (SEG1 to SEG396) and COM (COM1 to COM176) pins output the “ ...
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... HD66766R Setting flow for power supply and display instruction Power-on / off Sequence To prevent pulse lighting of LCD screens at power-on/off, the power-on/off sequence is activated as shown below. However, since the sequence depends on LCD materials to be used, confirm the conditions by using your own system. ...
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... HD66766R Power-off sequence Normal case Emergency case Vcc Power voltage : Vcc GND Vcc RESET GND V1OUT Driver SEG/COM output GND Note: When hardware reset is input during the power-off period, the D1-0 bits are cleared to "00" and SEG/COM output is forcibly lowered to the GND levels. ...
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... HD66766R Partial Sequence Setting Flow Normal display Display OFF Power supply setting change Display Duty change Frame frequency adjustment Display OFF more than 200ms Issue instruction for Step-up circuit output other mode setting stabilizing time Display On Partial display Figure 49 Normal to partial display Rev ...
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... HD66766R Oscillation Circuit The HD66766R can oscillate between the OSC1 and OSC2 pins using an internal R-C oscillator with an external oscillation resistor. Note that in R-C oscillation, the oscillation frequency is changed according to the external resistance value, wiring length, or operating power-supply voltage increased or power supply voltage is decreased, the oscillation frequency decreases. For the relationship between Rf resistor value and oscillation frequency, see the Electric Characteristics Notes section ...
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... HD66766R Frame-Frequency Adjustment Function The HD66766R has an on-chip frame-frequency adjustment function. The frame frequency can be adjusted by the instruction setting (DIV, RTN) during the LCD drive as the oscillation frequency is always the same. When the display duty is changed, the frame frequency can be adjusted to be the same. ...
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... HD66766R n-raster-row Reversed AC Drive The HD66766R supports not only the LCD reversed AC drive in a one-frame unit (B-pattern waveform) but also the n-raster-row reversed AC drive which alternates in an n-raster-row unit from one to 64 raster- rows (C-pattern waveform). When a problem affecting display quality occurs, such as cross-talk at high-duty driving of more than 1/64 duty, the n-raster-row reversed AC drive (C-pattern waveform) can improve the quality ...
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... HD66766R Screen-division Driving Function The HD66766R can select and drive two screens at any position with the screen-driving position registers (R14h and R15h). Any two screens required for display are selectively driven and a duty ratio is lowered by LCD-driving duty setting (NL4-0), thus reducing LCD-driving voltage and power consumption. For the 1st division screen, start line (SS17-10) and end line (SE17-10) are specified by the 1st screen-driving position register (R14h) ...
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... The following restrictions must be satisfied when setting the start line (SS17-10) and end line (SE17-10) of the 1st screen driving position register (R14h) and the start line (SS27-20) and end line (SE27-20) of the 2nd screen driving position register (R15h) for the HD66766R. occur if the restrictions are not satisfied. ...
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... HD66766R LCD Voltage Generation Circuit Figure 58 shows a configuration of the HD66766R LCD drive voltage generation circuit. It consists of step-up circuit 1 that doubles or triples the voltage that is applied to Vci1, step-up circuit 2 that multiplies the voltage from step-up circuit 1 by two to five times, and polarity circuit that generates a VCL level by inverting the VCH level centered around the VM level ...
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... HD66766R Notes: 1. Generate an output voltage (VOUT) from step-up circuit 1 within the range from 4.0 to 5.75V not allow the output voltage (VCH) from step-up circuit 2 to exceed not allow the output from Vci2 to exceed VOUT voltage . 4. When capacitor with polarity is used, be sure that an inverted voltage is not applied any state of the system ...
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... HD66766R How to determine the power setting value 1. Determine LCD drive bias Determine LCD drive bias first. LCD drive bias is theoretically (1/SQRT (display duty)) optimal; however, the total drive voltage can be reduced by lowering bias ratio. Consider the display quality, the drive voltage and the current consumption. ...
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... HD66766R Example 2: 1/176 duty ratio, Vcc = VREFL = 2.4V, Vci = 2.8V, 1/13 bias BS2-0 = H’8 : bias adjustment 1.4 times BT2-0 = H’4 : step-up circuit 1 BT3 = H’1 : operate voltage inverting circuit DC2-0 = H’6 : step-up circuit 1 frequency 32 clocks TBD AP1-0 = H’1 : low fixed current in the amplifier VC2-0 = H’4 : internal Vci1 regulator off VR3-0 = H’ ...
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... HD66766R power supply level correlation VC2-0 (0.92 to 0.68 times) VOUT (4.0 to 5.75 V) VREFM ( VOUT) Vcc BT0 Vci1 ( times) VREFL ( VCC) GND Figure 57 HD66766R Power supply level correlation Rev. 1.0-1 / September 2002 BT2 times) CT6-0 (contrast adjustment) Vci2 BS3-0 (0.5 to 2.165 times) VR2-0 (1.1 to 3.4 times) Voltage polarity ...
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... HD66766R Connection of condenser related to the magnification of step up circuit 1 (1) 2 times step-up circuit (2 x Vci1) VciOUT ‚ u ‚ ƒ ‚ ‰ 1.0 uF adjusting circuit Vci1 C11- C11+ VOUT 1 generating C12- step-up C12+ circuit 1 1.0 uF VOUT Figure 58 Connection of condenser related to the magnification of step up circuit 2 (1) 2 times step-up circuit (2 x Vci2) 1 ...
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... HD66766R Absolute Maximum Ratings Table 41 Item Symbol Power supply voltage (1) Vcc Power supply voltage (2) Vcil Power supply voltage (3) VCH –VCL Vt Input voltage Operating temperature Topr Storage temperature Tstg Notes the LSI is used above these absolute maximum ratings, it may become permanently damaged. ...
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... HD66766R DC Characteristics (V = 2.2 to 3.6 V, VCH-VCL=8V to 44V –40 to +85°C* CC Table 42 Item Symbol Unit Test Condition Input high voltage Input low voltage Output high voltage ( OH1 (DB0-15 pins) Output low voltage (1) (DB0-15 pins OL1 Driver ON resistance R k SEG (SEG pins) ...
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... HD66766R Step up circuit characteristics Table 43 Item Terminal Unit Test Condition VCC = 3.0 V Vci step up factor = 0.92 Step up VOUT V Step up factor : two times circuit 1 Step up cycle: 32 divided cycle Load voltage = 400 VCC = 3.0 V VOUT = 5.5 V VREFL = 3.0 V VREFM = 1.1 x VREFL Constant current of operation amplifier: small Step up VCH V Contrast adjustment value = 0.000R ...
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... HD66766R AC Characteristics (V = 2 –40 to +85°C* CC Table 44 Clock Characteristics (V = 2 Item Symbol Unit External clock frequency fcp kHz External clock duty ratio Duty % External clock rise time trcp µs External clock fall time tfcp µs R-C oscillation clock f kHz OSC ...
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... HD66766R Normal Write Mode (HWM=0) Table 47 (Vcc = 2.4 to 3.6 V) Item Enable cycle time Write Read Enable high-level pulse width Write Read Enable low-level pulse width Write Read Enable rise/fall time Set up time (RS, R CS*) Address hold time Write data set up time Write data hold time ...
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... HD66766R 80-system Bus Interface Timing Characteristics Normal Write Mode (HWM=0) Table 49 (Vcc = 2.2 to 2.4 V) Item Bus cycle time Write Read Write low-level pulse width Read low-level pulse width Write high-level pulse width Read high-level pulse width Write/Read rise/fall time Setup time (RS to CS*, WR*, RD*) ...
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... HD66766R Normal Write Mode (HWM = 0) Table 51 (Vcc = 2.4 to 3.6 V) Item Bus cycle time Write Read Write low-level pulse width Read low-level pulse width Write high-level pulse width Read high-level pulse width Write/Read rise/fall time Set up time (RS to CS*, WR*, RD*) Address hold time Write data setup time ...
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... HD66766R Clock Synchronized Serial Interface Timing Characteristics Table 53 (Vcc = 2.2 to 2.4 V) Item Write (received) Serial clock cycle time Read (transmitted) Write (received) Serial clock high-level pulse width Read (transmitted) Write (received) Serial clock low-level pulse width Read (transmitted) Serial clock rise/fall time ...
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... HD66766R Reset Timing Characteristics (V = 2 Table 55 Item Symbol Reset low-level width t RES Reset rise time t rRES Electrical Characteristics Notes 1. For bare die and wafer products, specified The following three circuits are I pin, I/O pin, O pin configurations. Pins: RESET*, CS*, E/WR, RW/RD, RS, ...
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... HD66766R 6. This excludes the current flowing through the input/output units. The input level must be fixed high or low because through current increases if the CMOS input is left floating. Even if the CS pin is low or high when an access with the interface pin is not performed, current consumption does not change. ...
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... HD66766R Step-up circuit loading characteristics (1) Step-up circuit 1 – loading characteristic Measureing condition Ta = 25C, VCC = 3.0 [V], Oscillation frequency = 250 [kHz] (2) Vci1 step-up magnification = 0.92, Step-up magnification two times 5.5 5.0 4.5 4.0 3.5 3.0 0 300 600 Load voltage [uA] Figure 69 Step-up circuit 1- load characteristic (AP=01 amplifier constant voltage: small) 5.5 5.0 4.5 4.0 3.5 3.0 0 300 600 Load voltage [uA] Figure 70 Step-up circuit 1- load characteristic (AP=10 amplifier constant voltage: medium) 5 ...
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... HD66766R (2) Step-up circuit 2 – loading characteristic Measureing condition Ta = 25C, VCC = 3.0 [V], Oscillation frequency = 250 [kHz] Vci1 step-up magnification = 0.92, Step-up circuit 1: step-up magnification two times 32 divided frequency, VREFM = 1.1 x VREFL 0.00R1/12 Bias Step-up circuit 2: Five times step-up 21.6 21.5 21.4 21.3 21.2 21 Load voltage [uA] Figure 72 Step-up circuit 2- load characteristic (AP=01 amplifier constant voltage: small) 21 ...
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... HD66766R (3) Polarity inversion circuit – loading characteristic Measureing condition Ta = 25C, VCC = 3.0 [V], Oscillation frequency = 250 [kHz] Vci1 step-up magnification = 0.92, Step-up circuit 1 step-up magnification two times 32 divided frequency, VREFM = 1.1 x VREFL 0.00R 1/12 Vias Step-up circuit 2: Five times 21.5 21.3 21.1 20.9 20.7 20 Load voltage [uA] Figure 75 Polarity inversion circuit – Load characteristic (AP=01 amplifier constant current: small) 21 ...
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... HD66766R Load Circuits AC Characteristics Test Load Circuits Data bus: DB15 to DB0 Test point 50pF Rev. 1.0-1 / September 2002 Figure 78 Load Circuit 91 ...
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... HD66766R Timing Characteristics 68-system Bus Operation VIH RS VIL R/W tASE CS* VIL E Note2) DB0 to DB15 Note 2) DB0 to DB15 Figure79 68-system Bus Timing Notes: 1) PWEH is specified in the overlapped period when CS* is low and E is high. 2) Parallel data transfer is enabled on the DB15-8 pins when the 8-bit bus interface is used. ...
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... HD66766R 80-system Bus Operation VIH RS VIL tAS CS* VIL WR * RD* tWRr DB0 to DB15 DB0 to DB15 Figure 80 80-system Bus Timing Note1) PWLW and PWLR are specified in the overlapped period when CS* is low and WR* or RD* is low. Note2) Parallel data transfer is enabled on the DB15-0 pins when the 8-bit bus interface is used. Fix the DB7-0 pins to Vcc or GND ...
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... HD66766R Clock Synchronized Serial Interface Operation Start: S CS* VIL tCSU SCL VIH VIL SDI tSOD SDO Figure 81 Clock Synchronized Serial Interface Timing Reset Operation RESET* VIL Rev. 1.0-1 / September 2002 tSCYC tscf tscr tSCL tSCH VIH VIH VIL VIL VIL tSISU tSIH ...
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... When HD66766R is mounted on glass, the grand terminal gets contact with resistance of ITO wiring. HD66766R has 8 GNDs, 4 AGNDs for power supply circuit, and another 4 GNDs for RAM and Logic. When all the GNDs are connected on glass with ITO, transferring display data to the internal RAM at high-speed causes high current consumption ...
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... HD66766R 0.6 0.5 0.4 0.3 0.2 0 Figure 2 VCH voltage decrease depending on RAM access frequency and Resistance of ITO wiring Vcc Vcc Vcc Vcc Vcc Vcc ITO Figure 3 Recommended ITO Connection Pattern (HCD667X66) Vcc Vcc Vcc Vcc AVcc AVcc ITO Figure 4 Recommended ITO Connection Pattern (HCD667X66R) Rev. 1.0-1 / September 2002 ...
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... HD66766R Maintenance history report Rev. Date Contents 1.0 August 8, 2002 First release 1.1 September 17, 2002 P74 2.Determine VOUT voltage Line2 From “4.0 to 5.5V” to “4.0 to 5.75 V” P74 5.Determine input voltage of step-up circuit2 Line 3 From “4.5 to 5.75V)-0.5V” to “ (4.0 to 5.75V)-0.5V Rev. 1.0-1 / September 2002 97 ...