hd66503 Renesas Electronics Corporation., hd66503 Datasheet
hd66503
Related parts for hd66503
hd66503 Summary of contents
Page 1
... It also achieves low current consumption of 100 µA through the CMOS process. Combined with the HD66520, a 160-channel column driver with an internal RAM, the HD66503 is optimal for use in displays for portable information tools. Features ...
Page 2
... HD66503 Pin Arrangement X240 X239 X238 X237 X236 X235 X234 X233 X232 X231 X10 Note : This figure does not specify the tape carrier package dimensions. 928 1 272 V2R 2 271 V5R 3 270 V6R 4 269 V1R 5 268 V EER 6 267 V CC2 7 266 M/S 8 265 DOC ...
Page 3
... During low level, the line alternating waveform is output from pin M. During high level, pin M outputs an EOR (exclusive OR) waveform between a line alternating waveform and frame alternating waveform. Set the pin to low during slave mode. See Table 3. HD66503 '2& ). See 1/240 display duty ratio 929 ...
Page 4
... Table 4. See Figure 2. However, when reset is performed during operation, RAM data in the HD66520 which is used together with the HD66503 may be destroyed. Therefore, write data to the RAM again. I/O 1 The bidirectional shift register shifts data at the falling edge of CL1. During ...
Page 5
... HD66520’s pin During slave mode, pin an input pin for display off control signal. In this case, connect this signal to the master HD66503’s pin Output 240 Selects one from among four levels (V1, V2, V5, and V6) depending on the combination of M signal and display data ...
Page 6
... HD66503 932 Figure 1 LCD Drive Levels 2. reset r 0 RESET 0 Figure 2 Reset Pin Operation M signal 1 0 Display data Output level Figure 3 LCD Drive Output ...
Page 7
... Min Typ 1.0 — — — Shift Direction of First Line Marker X240 X1 X1 X240 X120 X1, X240 X121 X1 X120, X121 X240 X240 X1 X1 X240 HD66503 Input/Output State Pin M State Input Output Max Unit — µs 200 ns 933 ...
Page 8
... HD66503 Internal Block Diagram V1L V6L V5L V2L V EEL V CC1 V CC2 GND DUTYS RESET CRP MSS CR oscillator 934 X1 to X240 LCD driver D1 to D240 Level Level shifter shifter L1 to L240 MP Bidirectional shift register SHLS FLMP CL1P LCD timing FLM1 generator ...
Page 9
... R When the external clock is used, input external clock to pin CR and open pins C and R (Figure 4). When using the HD66503 during slave mode, the operation clock will not be needed; therefore, connect pin and open pins C and R (Figure 5). ...
Page 10
... HD66503 5. Display Off Control Circuit: Controls display-off function by using external display off signal ',636 and automatic display off signal FLMM generated by the liquid crystal timing generator. Automatic display off signal FLMM is an internal signal that is used to turn off the display in four frames after signal reset is released ...
Page 11
... EOR (exclusive OR) of line alternating waveform and CC frame alternating waveform. CR 240 CL1 (120) FLM Figure 6 Generation of Signals CL1 and FLM (When MWS0 to MWS5 = 6) CL1 1 M (MEOR = GND) M (MEOR = FLM Figure 7 Generation of Signal HD66503 or GND (H or L). In addition 937 ...
Page 12
... HD66503 3. Auto Display-Off Control: This functions prevents incorrect display after reset release. The display is turned off four frames following after reset release. In addition, the display off control signal shown in '2& Figure 8 is output by pin . This pin is connected to pin RESET FLM DOC ...
Page 13
... COM240 COM241 to No. 2 COM480 HD66520 Note: Upper and lower displays are driven by separate HD66503s to ensure display quality. No. 1 operates in master mode, and No. 2 operates in slave mode. Figure 10 When Using Two HD66503s LCD When using the internal oscillator When using an external clock LCD No ...
Page 14
... HD66503 HD66503 Connection List Table 7 HD66503 Connection List 940 ...
Page 15
... LCD panel using segment driver HD66520 240 seg1 seg2 LCD seg159 seg160 Line scan direction X1 , X2, X3, X240 LCD driver / HD66503 6 DOC / LCD display timing control circuit 1 DISPOFF / M/S DUTY SHL V CC V1, V2, V5, V6 V1, V2, V3 DISPOFF / Power supply circuit HD66503 MWS0 to 5 MEOR RESET 941 ...
Page 16
... Figure 12 System Configuration (2) 942 320-dot LCD panel using segment driver HD66520 240 seg1 seg2 LCD seg159 seg160 seg161 seg162 seg319 seg320 Line scan direction X1, X2, X3, X240 LCD driver / HD66503 6 DOC / LCD display timing control circuit 1 DISPOFF / DUTY SHL M V1, V2, V5, V6 ...
Page 17
... Timing Chart (1) Figure 13 Timing Chart (1) HD66503 943 ...
Page 18
... HD66503 Example of System Configuration (3) Figure 14 shows a system configuration for a 320 with internal bit-map RAM. Refer to Timing Chart (2) for details A15 DB0 to DB7 CS, WE Power supply circuit V1, V2, V5, V6 Figure 14 System Configuration (3) 944 480-dot LCD panel using segment driver HD66520 ...
Page 19
... Timing Chart (2) HD66503 No. 1 HD66503 No. 2 Figure 15 Timing Chart (2) HD66503 945 ...
Page 20
... HD66503 Power Supply Circuit + –25V 0V Note: The values of R1 and R2 vary with the LCD panel used. When the bias factor is 1/15, for example, the values of R1 and R2 can be determined as follows: R1 4R1 + then Figure 16 Power Supply Circuit ...
Page 21
... EER Symbol Ratings V –0 – VT1 –0 0.3 CC VT2 V – –20 to +75 opr T –40 to +125 stg = V V1L = V1R CC1 CC2 HD66503 Unit Notes °C °C V6L = V6R V5L = V5R 947 ...
Page 22
... HD66503 Electrical Characteristics DC Characteristics (V = 2.7 to 5.5V Item Symbol Min Input high level VIH 0 voltage Input low level VIL 0 voltage Output high VOH V –0.4 CC level voltage Output low VOL — level voltage Driver “on” R — ON resistance Input leakage I –1.0 IL1 ...
Page 23
... Duty t rcp t fcp Figure 17 External Clock Figure 18 Timing Components is connected Oscillator is set as described in note 6. CC ',632 HD66503 Notes 100 pF, = 180 k –GND = 3V –V = 28V 5(6 and CR, , and M. TH 100 Min Typ Max Unit 45 50 ...
Page 24
... HD66503 10. This value is specified for the current flowing through GND under the following conditions: Each terminal of MEOR, MWS0 to MWS5, DUTY, SHL, 6 connected GND, and frequency of CL1, FLM respectively established as CC follows kHz 62.5 Hz, f CL1 FLM 11. This value is specified for the current flowing through V described in note 8 ...
Page 25
... LCD drive circuits’ output impedance is stable. Note that V depend on power ON supply voltages V –V . See Figure 21 Figure 21 Relationship between Driver Output Waveform level, and V5L/R and V2L/R should be near the V1L/R V6L/R 6.4 2.5 V5L V2L –V ( HD66503 EE 951 ...
Page 26
... HD66503 AC Characteristics (V = 2.7 to 5.5V Slave Mode (M/ = GND) Item Symbol CL1 high-level width t CWH CL1 low-level width t CWL FLM setup time t FS FLM hold time t FH CL1 rise time t r CL1 fall time t f Note: 1. Based on the load circuit shown in Figure 22. ...
Page 27
... Min Typ Max — — 1 — — 1 — — 500 t /2 – 500 — — osc t OSC DCL1 0 0 DFLM 0 0 Figure 24 Master Mode Timing HD66503 Unit Notes µs µ DCL1 t DFLM 953 ...