MK50H25DIP ST Microelectronics, Inc., MK50H25DIP Datasheet
MK50H25DIP
Related parts for MK50H25DIP
MK50H25DIP Summary of contents
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SECTION 1 - FEATURES System clock rate MHz (MK50H25 - 33), 25 MHz (MK50H25 - 25 MHz (MK50H25 - 16). Data rate Mbps continuous (MK50H25 - 33 Mbps ...
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MK50H25 DESCRIPTION (Continued) For added flexibility a transparent mode provides an HDLC transport mechanism without link layer support. This flexible transparent mode may be easily entered and exited without affecting the X.25 link status or the link state variables kept ...
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PLCC52 PIN CONNECTION (Top view DAL02 DAL01 DAL00 READ INTR DALI DALO DAS BMO/BYTE/BUSREL No Connect BM1/BUSAKO HOLD/BUSRQ ALE/ DAL13 DAL14 DAL15 A16 A17 A18 MK50H25Q A19 A20 A21 A22 No Connect ...
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MK50H25 TAble 1: PIN DESCRIPTION LEGEND: I Input only IO Input / Output OD Open Drain (no internal pull-up) Note: Pin out for 52 pin PLCC is shown in brackets. SIGNAL NAME PIN(S) TYPE DAL<15:00> 2-9 IO/3S 40-47 [2-10 44-51] ...
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Table 1: PIN DESCRIPTION (continued) SIGNAL NAME PIN(S) TYPE HOLD 17 IO/OD BUSRQ [19] ALE 18 O/3S AS [20] HLDA 19 I [21 [22] ADR 21 I [23] READY 22 IO/OD [24] DESCRIPTION If CSR4<00> BCON = ...
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MK50H25 Table 1: PIN DESCRIPTION (continued) SIGNAL NAME PIN(S) TYPE RESET 23 I [25] TCLK 25 I [28] DTR 26 IO RTS [29] RCLK 27 I [30] SYSCLK 28 I [31 [32] DSR 30 IO CTS [33] ...
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Figure 1: Possible System Configuration for thr MK50H25 MEMORY (MULTIPLE DATA BLOCKS) HOST PROCESSOR (68000, 80186, Z8000, ETC) 16-BIT DATA BUS INCLUDING 24-BIT ADDRESS AND BUS CONTROL MK50H25 LINE DRIVERS AND RECEIVERS ELECTRICAL I/O (SUCH AS RS-232C, RS-423, RS-422) DATA ...
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MK50H25 Figure 2: MK50H25 Simplified Block Diagram DMA CONTROLLER SYSCLK RECEIVER FIFO RCLK RECEIVER RD 8/64 READY READ DAS FIRMWARE CONTROL / STATUS MICRO REGISTERS CONTROLLER INTERNAL BUS TRANSMITTER FIFO VCC VSS - GND RESET TCLK TRANSMITTER ...
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Functional Blocks Refer to the block diagram in Figure 2. The MK50H25 is primarily initialized and control- led through six 16-bit Control and Status Regis- ters (CSR0 thru CSR5). The CSR’s are accessed through two bus addressable ports, the ...
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MK50H25 FWM of being full (by DMA from TX buffer in shared memory), the transmit FIFO will not inter- rupt the microcontroller until it empties enough to fall below the watermark level. The transmit FIFO also has a selectable Transmit ...
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If the frame is too long for one buffer, the next buffer will be used after filling the first buffer; that is, ”chained”. The MK50H25 will then ”look ahead” to the next buffer, ...
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MK50H25 Table A - MK50H25 Command/Response Repertoire FORMAT COMMAND Information Transfer I Supervisory RR RNR REJ * Unnumbered UI SABM DISC * XID TEST Table B - MK50H25 Command/Response Repertoire FORMAT COMMAND RESPONSE ENCODING Information I I Transfer Supervisory RR ...
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Figure 3: MK50H25 Memory Management Structure CSR 2, CSR3 POINTER TO INITIALIZATI ON BLOCK INITIALIZATI ON BLOCK MODE FRAME ADDRESS FIELDS TIMER VALUES RX DESCRIPTOR POINTER TX DESCRIPTOR POINT ER XID/TEST TRANSMIT DESCRIPTOR POINTER XID/TEST RECEIVE DESCRIPTOR POINTER STATUS BUFFER ...
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MK50H25 SECTION 4 PROGRAMMING SPECIFICATION This section defines the Control and Status Reg- isters and the memory data structures required to program the MK50H25. 4.1 Control and Status Registers There are six Control and Status Registers (CSR’s) resident within the ...
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Register Data Port (RDP BIT NAME 15:00 CSR DATA Writing data to the RDP loads data into the CSR selected by RAP. Reading the data from RDP reads the ...
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MK50H25 4.1.2 Control and Status Register Definition 4.1.2.1 Control and Status Register 0 (CSR0) RAP<3:1> BIT NAME DESCRIPTION 15 TDMD ...
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INEA INTERRUPT ENABLE allows the INTR I/O pin to be driven low when the Interrupt Flag is set. If INEA = 1 and INTR = 1 the INTR I/O pin will be low. If INEA = 0 the INTR ...
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MK50H25 cleared by writing a ”1” into the bit. Writing a ”0” has no effect also cleared by Bus RESET or by issuing a Stop primitive. 01 RINT RECEIVER INTERRUPT is set after the MK50H25 updates an entry ...
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Init: Instructs the MK50H25 to read the Initialization Block from memory. Valid only in the Stopped mode or phase. This should be performed prior to the Start primitive after a bus reset or power-up. 3 Trans: Instructs MK50H25 to ...
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MK50H25 ONLY and is set by the chip and cleared by writing a ”1” to the bit or by Bus RESET. Under normal operation the host should clear the PAV bit after PPRIM is read. 05:04 PPARM PROVIDER PARAMETER provides ...
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XID command is located in the XID/TEST Receive buffer. Valid only if XIDE bit in CSR2 is set. 11 XID Confirmation: Indicates the receipt of an XID response. The data field of the XID command is located in ...
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MK50H25 07:00 IADR The high order 8 bits of the address of the first word (lowest address) in the Initialization Block. IADR must be written by the Host prior to issuing an INIT primitive. 4.1.2.4 Control and Status Register 3 ...
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FWM These bits define the FIFO watermarks. FIFO watermarks prevent the MK50H25 from performing DMA transfers to/from the data buffers until the FIFOs contain a minimum amount of data or space for data. For re- ceive, data will only ...
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MK50H25 01 ACON ALE CONTROL defines the assertive state of pin 18 when the MK50H25 is a Bus Master. ACON is READ/ WRITE and cleared by Bus RESET. 00 BCON BYTE CONTROL redefines the Byte Mask and Hold I/O pins. ...
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DSR DATA SET READY is used to control or observe the DSR I/O pin depending on the value of DSRD. If DSRD = 0, this bit be- comes READ ONLY and always equals the current value of the DSR/CTS ...
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MK50H25 4.2 Initialization Block MK50H25 initialization includes the reading of the Initialization Block in the off-chip memory to obtain the operating parameters. The Initialization Block is defined below. Upon receiving an Init primitive, portions of the Initialization block are read ...
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Mode Register The Mode Register allows alteration of the MK50H25’s operating parameters MFS IADR + 00 <4:0> BIT NAME DESCRIPTION 15:11 MFS<4:0> Minimum Frame Spacing defines the minimum number of flag sequences transmitted MK50H25. This ...
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MK50H25 depending on FCSS, but no whether the FCS is correct. If the received frame has no FCS, then the FCSEN bit (in IADR+16) should be set so that MCNT will reflect the correct length of the received frame. 04 ...
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Station Address and Control Field Filtering The Local and Remote frame addresses may be either one or two octets according to the EXTA control bit described in the MODE register. If extended address mode filtering is selected, bit zero ...
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MK50H25 Table 3: Address and Control Field Handling By The MK50H25 Receiver In Transparent Mode DACE PROM EXTA EXTAF EXTC ...
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Timer/Counters 1 5 IADR + 06 IADR + 08 IADR + 10 IADR + 12 IADR + 14 There are 5 independent counter-timers. The Host will write the value of these to the Initialization Block. COUNTER DESCRIPTION N1 MAXIMUM ...
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MK50H25 TP TRANSMIT POLLING TIMER. This scaled timer determines the length of time between polls of the Transmit Descriptor Ring to determine if there is a frame awaiting transmis- sion (i.e. OWNA bit has been set plus other appropriate information ...
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Receive Descriptor Ring Pointer IADR + 16 RLEN IADR + 18 BIT NAME DESCRIPTION 15 RINTD RECEIVE INTERRUPT DISABLE. Setting this bit will cause no Receive Interrupt (RINT ...
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MK50H25 14:12 TLEN TRANSMIT RING LENGTH is the number of entries in the Transmit Ring expressed as a power of two Reserved, must be written as a zero. 10:08 TWD Transmit Window is the window size of the ...
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Error Counters Seven locations in the Initialization buffer are reserved for use as error counters which the MK50H25 will increment. These counters are intended for use by the host CPU for statistical analysis. The MK50H25 will only increment the ...
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MK50H25 11 UIR UI Received indicates a UI frame has been received and is in this buffer. 10 FRMRR FRMR Received indicates the I-field of a FRMR is stored in this buffer. In Transparent mode with RBFCS=1 (IADR+16) it indicates ...
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Receive Message Descriptor 3 (RMD3 BIT NAME DESCRIPTION 15:00 MCNT Message Byte Count is the length, in bytes, of the received frame MCNT is valid only when ELF is set to a one. ...
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MK50H25 11 TUI Transmit a UI frame indicates that a UI frame transmitted from the transmit buffer instead of a normal I frame. This bit must be set for anything transmitted in Transparent Mode. 10 TINTD Transmit ...
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Transmit Message Descriptor 3 (TMD3 BIT NAME DESCRIPTION 15:00 MCNT Message byte count is the length, in octets, of the data contained in the corresponding buffer. The value of this field is expressed ...
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MK50H25 MK50H25 STATUS BUFFER FIELD DESCRIPTION V(r) Current value of the Receive Count Variable. 0 < V(r) < < V(r) < 127 for extended control). V(s) Current value of the Transmit Count Variable. 0 < V(s) < 7 ...
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Active Link Setup The following procedure should be followed to actively establish a link. 1. Issue Connect Request primitive (UPRIM=6) through CSR1. The MK50H25 will attempt to establish a logical link. It does this by sending a SABM/P=1 frame, ...
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MK50H25 4.4.8 Link Reset The following procedure should be followed to reset an established link. 1. Issue a Reset Request primitive (UPRIM=8). 2. Wait for a Reset Confirmation primitive (PPRIM=9) from the MK50H25 (indicating reception of UA frame in response ...
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MK50H25 Internal Self Test The MK50H25 contains an easy to use internal self test designed to test, with a high fault coverage, all of the major blocks of the device except the DMA controller suggested that a ...
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ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Symbol T Temperature Under Bias UB T Storage Temperature stg V Voltage on any pin with respect to ground G P Power Dissipation tot Stresses above those listed under ”Absolute Maximum Rating” may cause permanent ...
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MK50H25 AC TIMING SPECIFICATIONS (Continued) - MK50H25 - percent, unless otherwise specified Signal Symbol 13 RCLK T RCLK period RCT 14 RCLK T RCLK high ...
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AC TIMING SPECIFICATIONS (Continued) - MK50H25 - percent, unless otherwise specified Signal Symbol 49 DALO T DALO setup time (Bus Master read) ROS 50 DALO ...
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MK50H25 AC TIMING SPECIFICATIONS (Continued) - MK50H25 - percent, unless otherwise specified Signal Symbol 13 RCLK T RCLK period RCT 14 RCLK T RCLK high ...
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AC TIMING SPECIFICATIONS (Continued) - MK50H25 - percent, unless otherwise specified Signal Symbol 49 DALO T DALO setup time (Bus Master read) ROS 50 DALO ...
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MK50H25 AC TIMING SPECIFICATIONS (Continued) - MK50H25 - percent, unless otherwise specified Signal Symbol 13 RCLK T RCLK period RCT 14 RCLK T RCLK high ...
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AC TIMING SPECIFICATIONS (Continued) - MK50H25 - percent, unless otherwise specified Signal Symbol 49 DALO T DALO setup time (Bus Master read) ROS 50 DALO ...
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MK50H25 Figure 5a: TTL Output Load Diagram TEST POINT FROM OUTPUT UNDER TEST 0 NOTE: This load is used on all outputs except INTR, HOLD, READY. Figure 6: MK50H25 Serial Link Timing Diagram RCLK RD TCLK 12 ...
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Figure 7: MK50H25 BUS Master Timing (Read) (for CYCLE = 0, CSR2<15>) SYSCLK 64 HOLD 24 HLDA A 16-23 ALE DAS READY DAL0-15 DALO 45 DALI READ BM0,1 NOTES: 1. The shaded SYSCLK periods T0 and T5 will be removed ...
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MK50H25 Figure 7a: MK50H25 Reduced Cycle BUS Master Timing (Read) (for CYCLE = 1, CSR2<15>) SYSCLK 64 HOLD 24 HLDA 27 A 16-23 23 ALE 23 DAS READY DAL0-15 DALO 45 DALI READ BM0,1 NOTES: 1. This reduced DMA Cycle ...
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Figure 8: MK50H25 BUS Master Timing Diagram (Write) (for CYCLE = 0, CSR2<15>) SYSCLK 64 HOLD 24 HLDA 27 A 16-23 23 ALE 23 DAS READY DAL0-15 DALO 45 DALI READ BM0,1 NOTES: 1. The shaded SYSCLK periods T0 and ...
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MK50H25 Figure 8a: MK50H25 Reduced Cycle BUS Master Timing (Write) (for CYCLE = 1, CSR2<15>) SYSCLK HOLD 24 HLDA 27 A 16-23 23 ALE 23 DAS READY DAL0-15 DALO 45 DALI READ BM0,1 NOTES: 1. This Reduced DMA Cycle Time ...
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Figure 8b: BUS Master BURST Timing (Reduced Cycle - Write SYSCLK 64 HOLD 24 25 HLDA 27 A 16-23 23 ALE 23 DAS READY 29 DAL0-15 ADDR 33 DALO 45 DALI READ BM0 ...
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MK50H25 Figure 9: MK50H25 BUS Slave Timing Diagram (Read) SYSCLK CS ADR DAS READY READ (Read) DAL 0-15 NOTES: 1. Input setup and hold times are in minimum values required to or from the particular edge specified in order to ...
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Figure 10: MK50H25 BUS Slave Timing Diagram (Write) SYSCLK CS ADR DAS READY READ (Write) DAL0-15 NOTES: 1. Input setup and hold times are the minimum values required to or from the particular edge specified in order to be recognized ...
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MK50H25 ORDERING INFORMATION MK50H25 Q XX PACKAGE N = Plastic DIP (48 Pins Plastic J-Leaded Cip Carrier (52 Pins) -84Q = 84 PLCC for use with external ROM PART# PROTOCOL 50H25 = LAPB 59/64 SPEED SORT 16 = ...
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DIP48 PACKAGE MECHANICAL DATA DIM. MIN. TYP. a1 0.63 b 0.45 b1 0. 15.2 e 2.54 e3 58. 4.445 L mm MAX. MIN. 0.31 0.009 62.74 16.68 0.598 14.1 3.3 MK50H25 inch TYP. MAX. ...
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MK50H25 PLCC52 PACKAGE MECHANICAL DATA DIM. MIN. TYP. A 4.20 A1 0.51 A3 2.29 B 0.33 B1 0.66 C 0.25 D 19.94 D1 19.05 D2 17.53 D3 15.24 E 19.94 E1 19.05 E2 17.53 E3 15.24 e 1.27 L 0.64 ...
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PLCC84 PACKAGE MECHANICAL DATA See following page for PLCC84 pin description DIM. MIN. TYP. A 4.20 A1 0.51 A3 2.29 B 0.33 B1 0.66 C 0.25 D 30.10 D1 29.21 D2 27.69 D3 25.40 E 30.10 E1 29.21 E2 27.69 ...
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MK50H25 MK50H25 PLCC84 Pin Description PIN SIGNAL NAME 1 Vss 2 EROMEN - External ROM Enable 3 DAL07 DAL06 6 EROMD11 7 DAL05 8 DAL04 9 DAL03 10 EROMD10 11 DAL02 12 DAL01 13 DAL00 14 EROMD09 ...
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Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its ...