MK50H27DIP ST Microelectronics, Inc., MK50H27DIP Datasheet
MK50H27DIP
Related parts for MK50H27DIP
MK50H27DIP Summary of contents
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SECTION 1 - FEATURES Complete Level 2 Implementation of SS7. Compatible with 1988 CCITT, AT&T, ANSI, and Bellcore Signalling System Number 7 link level protocols. Optional operation to comply with Japanese TTC JT-Q703 specification requirements Pin-for-pin and architecturally compatible with ...
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MK50H27 INTRODUCTION (Continued) and out of memory through the Host’s bus. A possible system configuration for the MK50H27 is shown in figure 1. For added flexibility a transparent mode provides an HDLC transport mechanism without link layer support. In this ...
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PLCC52 PIN CONNECTION (Top view DAL02 DAL01 DAL00 READ INTR DALI DALO DAS BMO/BYTE/BUSREL No Connect BM1/BUSAKO HOLD/BUSRQ ALE/ DAL13 DAL14 DAL15 A16 A17 A18 MK50H27Q A19 A20 A21 A22 No Connect ...
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MK50H27 TAble 1 - PIN DESCRIPTION LEGEND: I Input only IO Input / Output OD Open Drain (no internal pull-up) Note: Pin out for 52 pin PLCC is shown in brackets. SIGNAL NAME PIN(S) TYPE DAL<15:00> 2-9 IO/3S 40-47 [2-10 ...
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Table 1: PIN DESCRIPTION (continued) SIGNAL NAME PIN(S) TYPE HOLD 17 IO/OD BUSRQ [19] ALE 18 O/3S AS [20] HLDA 19 I [21 [22] ADR 21 I [23] READY 22 IO/OD [24] DESCRIPTION If CSR4<00> BCON = ...
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MK50H27 Table 1: PIN DESCRIPTION (continued) SIGNAL NAME PIN(S) TYPE RESET 23 I [25] TCLK 25 I [28] DTR 26 IO RTS [29] RCLK 27 I [30] SYSCLK 28 I [31 [32] DSR 30 IO CTS [33] ...
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Figure 1: Possible System Configuration for thr MK50H27 MEMORY (MULTIPLE DATA BLOCKS) HOST PROCESSOR (68020, i960, Z8000, ETC) 16-BIT DATA BUS INCLUDING 24-BIT ADDRESS AND BUS CONTROL MK50H27 LINE DRIVERS AND RECEIVERS ELECTRICAL I/O (SUCH AS RS-232C, RS-423, RS-422) DATA ...
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MK50H27 Figure 2: MK50H27 Simplified Block Diagram DMA CONTROLLER SYSCLK RECEIVER FIFO RCLK RECEIVER RD 8/56 READY READ DAS FIRMWARE CONTROL / STATUS MICRO REGISTERS CONTROLLER INTERNAL BUS TRANSMITTER FIFO VCC VSS - GND RESET TCLK TRANSMITTER ...
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Functional Blocks Refer to the block diagram in Figure 2. The MK50H27 is primarily initialized and control- led through six 16-bit Control and Status Regis- ters (CSR0 thru CSR5). The CSR’s are accessed through two bus addressable ports, the ...
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MK50H27 The transmit FIFO has a watermark scheme simi- lar to the one described for the receive FIFO above, and uses the same FWM value selections in CSR4 for the watermark. Once filled to within FWM of being full (by ...
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The starting address for the Initialization block, IADR, is de- fined in the CSR2 and CSR3 registers inside the MK50H27. 3.2.3 Signal Unit Repertoire The frame format supported by the MK50H27 is shown in Table ...
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MK50H27 TABLE A - MK50H27 Signal Unit Repertoire Message Signal Unit (MSU SIF 8 16/32 8n,n>=2 Link Status Signal Unit (LSSU 16/32 8/16 Values for SF SIO, Out of alignment 1 - SIN, ...
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Figure 3: MK50H27 Memory Management Structure CSR 2, CSR3 POINTER TO INITIALIZAT ION BLOCK INITIALIZAT ION BLOCK MODE TIMER VALUES PROTOCOL PARAMETERS RX DESCRIPTOR POINTER TX DESCRIPTOR POINTER STATUS BUFFER ADDRES S STATISTIC S STATUS BUFFER RECEIVER DESCRIPTOR RINGS DESCRIPTOR ...
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MK50H27 SECTION 4 PROGRAMMING SPECIFICATION This section defines the Control and Status Reg- isters and the memory data structures required to program the MK50H27. 4.1 Control and Status Registers There are six Control and Status Registers (CSR’s) resident within the ...
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Register Data Port (RDP BIT NAME 15:00 CSR DATA Writing data to the RDP loads data into the CSR selected by RAP. Reading the data from RDP reads the ...
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MK50H27 4.1.2.1 Control and Status Register 0 (CSR0) BIT NAME DESCRIPTION 12 DRX Disable the Receiver prevents the MK50H27 from further access to the Receiver Descriptor Ring. No received signal units are accepted after finishing reception of any signal unit ...
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TUR TRANSMITTER UNDERRUN indicates that the MK50H27 has aborted a signal unit since data was late from memory. This condition is reached empty while transmitting a signal unit. When TUR is set, an interrupt is generated if INEA = ...
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MK50H27 to continuouslytransmit SIOS signal units. 2 Init: instructs the MK50H27 to read the initialization block from memory. Valid only in the Power Off mode. 3 Trans: instructs the MK50H27 to enter the HDLC Transparent phase of operation. Data frames ...
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SIOS can be resumed by issuing UPRIM 16 described above. Valid only in Out Of Service phase when JSS7E=1 (CSR2). 07 PLOST PROVIDER PRIMITIVE LOST is set by MK50H27 when a provider primitive cannot be issued because the ...
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MK50H27 the receipt of an MSU after having entered congestion. This primitive indicates that the remote node congestion has abated ...
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Control and Status Register 4 (CSR4 CSR4 allows redefinition of the bus master interface. RAP<3:1> ...
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MK50H27 ”Non-data DMA transfers refers to any DMA transfers that access memory other than the data buffers themselves. This includes the Initialization Block, Descriptors, and Status Buffer. It has no effect on data DMA transfers. BSWPC allows the MK50H27 to ...
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Control and Status Register 5 (CSR5) CSR5 facilitates control and monitoring of modem controls. RAP<3:1> BIT NAME 15:05 0 Reserved, must be written as zeroes. ...
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MK50H27 4.2 Initialization Block MK50H27 initialization includes the reading of the initialization block in memory to obtain the operating parameters. The Initialization Block is defined below. Upon receiving an Init primitive, por- tions of the Initialization block are read by ...
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Mode Register The Mode Register allows alteration of the MK50H27’s operating parameters MFS IADR + 00 <4:0> BIT NAME DESCRIPTION 15:11 MFS<4:0> Minimum Frame Spacing defines the minimum number of flag sequences transmitted between adjacent ...
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MK50H27 05 DRCK Disable Receiver CK. When DRCK = 0, the receiver will extract and check the CK field at the end of each signal unit. When DRCK = 1, the receiver continues to extract the last ...
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T3 ALIGNED TIMEOUT TIMER PERIOD. T3 determines the maximum time the MK50H27 will wait in the ALIGNED state before signalling link failure. Represented as two’s complement. T4n NORMAL PROVING PERIOD. T4n determines the length of the normal proving period as ...
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MK50H27 IADR + 02 IADR + 04 IADR + 06 IADR + 08 IADR + 10 IADR + 12 IADR + 14 IADR + 16 IADR + 18 IADR + 20 IADR + 22 IADR + 24 28/ ...
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Protocol Parameters IADR + 26 IADR + 28 IADR + 30 IADR + 32 IADR + 34 PARM DESCRIPTION PO PROTOCOL OPTIONS. Defines the SS7 protocol options to be used. BIT NAME 00 DBUSY DBUSY = 1: Disables busy ...
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MK50H27 T / TTC D SUERM THRESHOLD. Number of consecutive signal units received in error that will cause an error rate high indication. When operating in TTC compliant mode (CSR2 JSS7E=1), this field should contain the D value (typically 16) ...
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Receive Descriptor Ring Pointer IADR + 36 0 RLEN IADR + 38 BIT NAME DESCRIPTION 15 0 Reserved, must be written as a zero. 14:12 RLEN RECEIVE RING LENGTH is the number of entries in ...
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MK50H27 4.2.5 Transmit Descriptor Ring Pointer (continued) BIT NAME DESCRIPTION 15 0 Reserved, must be written as a zero. 14:12 TLEN TRANSMIT RING LENGTH is the number of entries in the Transmit Ring expressed as a power of two. 11:08 ...
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Reserved IADR + 48 BIT NAME DESCRIPTION 15:00 0 Reserved, must be written as zeroes. 4.2.8 Statistics A significant portion of the initialization buffer is reserved for statistical information collected by the MK50H27. When a ...
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MK50H27 4.3 Receive and Transmit Descriptor Rings Each descriptor ring in memory word entry. The following is the format of the receive and transmit descriptors. 4.3.1 Receive Message Descriptor Entry 4.3.1.1 Receive Message Descriptor 0 (RMD0) 1 ...
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Receive Message Descriptor 1 (RMD1 BIT NAME DESCRIPTION 15:01 RBADR The low order 16 address bits of the receive buffer pointed to by this descriptor. RBADR is ...
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MK50H27 4.3.2 Transmit Message Descriptor Entry 4.3.2.1 Transmit Message Descriptor 0 (TMD0 BIT NAME DESCRIPTION 15 OWNA When this bit is a zero ...
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Transmit Message Descriptor 2 (TMD2 BIT NAME DESCRIPTION 15:00 SUL Signal Unit Length. Only required when in the first descriptor of a signal unit (SLF = 1) and when ...
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MK50H27 Figure 4a: MK50H27 Status Buffer SBA + SBA + 02 FSNT/FSNC B T SBA + 04 SBA + 06 SBA + 08 SBA + ...
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Status Buffer FIELD DESCRIPTION BIBT The value of the last BIB transmitted. BSNT The value of the last BSN transmitted. 0 BIBR The value of the last BIB received. BSNR The value of the last BSN received. 0 FIBT ...
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MK50H27 4.4 Detailed Programming Procedures 4.4.1 Initialization The following procedure should be followed to intialize the MK50H27: 1. Setup bus control information in CSR4. 2. Setup the Initialization Block and Desciptor Rings. 3. Load the address of the initialization block ...
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MK50H27 Internal Self Test The MK50H27 contains an easy to use internal self test designed to test, with a high fault coverage, all of the major blocks of the device except the DMA controller suggested that a ...
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MK50H27 ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Symbol T Temperature Under Bias UB T Storage Temperature stg V Voltage on any pin with respect to ground G P Power Dissipation tot Stresses above those listed under ”Absolute Maximum Rating” may cause ...
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AC TIMING SPECIFICATIONS CONTINUED - MK50H27 - percent, unless otherwise specified Signal Symbol 13 RCLK T RCLK period RCT 14 RCLK T RCLK high time ...
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MK50H27 AC TIMING SPECIFICATIONS CONTINUED - MK50H27 - percent, unless otherwise specified Signal Symbol 49 DALO T DALO setup time (Bus Master read) ROS 50 ...
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Figure 5a: TTL Output Load Diagram TEST POINT FROM OUTPUT UNDER TEST 0 NOTE: This load is used on all outputs except INTR, HOLD, READY. Figure 6: MK50H27 Serial Link Timing Diagram RCLK RD TCLK 12 TD ...
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MK50H27 Figure 7: MK50H27 BUS Master Timing (Read) (for CYCLE = 0, CSR2<15>) SYSCLK 64 HOLD 24 HLDA A 16-23 ALE DAS READY DAL0-15 DALO 45 DALI READ BM0,1 NOTES: 1. The shaded SYSCLK periods T0 and T5 will be ...
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Figure 7a: MK50H27 Reduced Cycle BUS Master Timing (Read) (for CYCLE = 1, CSR2<15>) SYSCLK 64 HOLD 24 HLDA 27 A 16-23 23 ALE 23 DAS READY DAL0-15 DALO 45 DALI READ BM0,1 NOTES: 1. This reduced DMA Cycle Time ...
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MK50H27 Figure 8: MK50H27 BUS Master Timing Diagram (Write) (for CYCLE = 0, CSR2<15>) SYSCLK 64 HOLD 24 HLDA 27 A 16-23 23 ALE 23 DAS READY DAL0-15 DALO 45 DALI READ BM0,1 NOTES: 1. The shaded SYSCLK periods T0 ...
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Figure 8a MK50H27 Reduced Cycle BUS Master Timing (Write) (for CYCLE = 1, CSR2<15>) SYSCLK HOLD 24 HLDA 27 A 16-23 23 ALE 23 DAS READY DAL0-15 DALO 45 DALI READ BM0,1 NOTES: 1. This Reduced DMA Cycle Time is ...
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MK50H27 Figure 8b: BUS Master BURST Timing (Reduced Cycle - Write SYSCLK 64 HOLD 24 25 HLDA 27 A 16-23 23 ALE 23 DAS READY 29 DAL0-15 ADDR 33 DALO 45 DALI READ BM0,1 50/56 T ...
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Figure 9: MK50H27 BUS Slave Timing Diagram (Read) SYSCLK CS ADR DAS READY READ (Read) DAL 0-15 NOTES: 1. Input setup and hold times are in minimum values required to or from the particular edge specified in order to be ...
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MK50H27 Figure 10: MK50H27 BUS Slave Timing Diagram (Write) SYSCLK CS ADR DAS READY READ (Write) DAL0-15 NOTES: 1. Input setup and hold times are the minimum values required to or from the particular edge specified in order to be ...
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ORDERING INFORMATION MK50H27 Q XX PACKAGE N = Plastic DIP (48 Pins Plastic J-Leaded Chip Carrier (52 Pins) PART# PROTOCOL 50H27 = SS7 Layer 2 protocol SPEED SORT 25 = 25MHz SYSCLK MK50H27 53/56 ...
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MK50H27 DIP48 PACKAGE MECHANICAL DATA DIM. MIN. TYP. a1 0.63 b 0.45 b1 0. 15.2 e 2.54 e3 58. 4.445 L 54/56 mm MAX. MIN. 0.31 0.009 62.74 16.68 0.598 14.1 3.3 inch TYP. ...
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PLCC52 PACKAGE MECHANICAL DATA DIM. MIN. TYP. A 4.20 A1 0.51 A3 2.29 B 0.33 B1 0.66 C 0.25 D 19.94 D1 19.05 D2 17.53 D3 15.24 E 19.94 E1 19.05 E2 17.53 E3 15.24 e 1.27 L 0.64 L1 ...
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MK50H27 Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from ...